Product specifications

VT1211 LPC SuperIO and Hardware Monitor
Revision 1.0 January 8, 2002 -6- Pinouts
Technologies, Inc.
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Pin Descriptions
Table 2. Pin Descriptions
LPC BUS INTERFACE
Signal Name Pin # Type Description
LRESET#
28 I
LPC Reset.
LFRAME#
27 O
LPC Frame. This signal indicates the start of an LPC cycle.
LAD[3:0]
23-26 I
LPC Address / Data 3-0. 4-bit LPC address / bidirectional data lines. LAD0 is the lsb.
LDRQ#
20 I
LPC DMA Request. An encoded signal for DMA channel select. Since there are three
DMA devices in the Super I/O module (VFIR, FDC, and ECP-mode parallel port), the LPC
Interface must provide LDRQ encoding for reflecting DREQ[3:0] status. Two LDRQ
messages or different DMA channels may be issued back-to-back for fast tracing DMA
requests. However, four PCI clocks will be inserted between two LDRQ messages of the
same DMA channel to guarantee that there is at least 10 PCI clocks for one DMA request to
change its status (the LPC Host will decode these LDRQ messages and send decoded
DREQn to the legacy DMA controller which runs off 4MHz or 33/8 MHz).
SERIRQ
21 IO
Serial IRQ.
PCICLK
19 I
LPC Clock. 33 MHz PCI clock input.
LPC Transactions
The LPC interface in the VT1211 supports LPC Host I/O Read / Write and DMA Read / Write transactions for the Super I/O
module. For LPC Host I/O Read or Write transactions, the Super I/O module processes a positive decoding, and the LPC interface
can depend on its result to respond to the current transaction via sending out SYNC values on the LAD[3:0] signals or leaving
LAD[3:0] in a tri-state condition. For DMA Read or Write transactions, the LPC interface depends on DMA requests from the
DMA devices in the Super I/O module, and may decide to ignore the current transaction or not.
The Floppy Controller (FDC) and Parallel Port (for ECP transactions) are 8 bit DMA devices, so if the LPC Host tries to initiate a
DMA transaction with a data size of 16 or 32 bits, the LPC interface will process the first 8 bit data and response with a SYNC
ready (0000b) which will terminate the DMA burst. Then the LPC interface will re-issue another LDRQ message to assert DREQi
after finishing the current DMA transaction.
MUX /
Latches
LDRQ Encoding
+ Sync./Monitor
ISA DMA
State Machine
Configuration
Trigger
ISA PIO
State Machine
LPC
Interface
State
Machine
Configuration
DACKn#
AEN, TC
IOR#, IOW#
IOCHRDY
LAD[3:0]
SIO_SEL
LAD_OE
SA[15:0]
SD[7:0]
CMD, StartLatch/select
LFRAME#
PCICLK
LRESET#
DREQn
LDRQ#
Figure 2. LPC Interface Block Diagram