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Low Pin Count

Super I/O

And Hardware Monitor

Revision 1.0

January 8, 2002

VIA TECHNOLOGIES, INC.

Summary of content (66 pages)

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Low Pin Count Super I/O And Hardware Monitor Revision 1.0 January 8, 2002 VIA TECHNOLOGIES, INC.
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Copyright Notice: Copyright © 2000, 2001, 2002 VIA Technologies Incorporated. Printed in the United States. ALL RIGHTS RESERVED. No part of this document may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language, in any form or by any means, electronic, mechanical, magnetic, optical, chemical, manual or otherwise without the prior written permission of VIA Technologies Incorporated. VT1211 may only be used to identify a product of VIA Technologies, Inc.
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Technologies, Inc. VT1211 LPC SuperIO and Hardware Monitor We Connect REVISION HISTORY Document Release 1.0 Date 1/8/02 Revision 1.0 January 8, 2002 Revision Initial release (same as internal rev 0.
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Technologies, Inc. VT1211 LPC SuperIO and Hardware Monitor We Connect TABLE OF CONTENTS REVISION HISTORY .......................................................................................................................................................................I TABLE OF CONTENTS ................................................................................................................................................................. II LIST OF FIGURES ....................................
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Technologies, Inc. VT1211 LPC SuperIO and Hardware Monitor We Connect ROM Registers (LDN D)...................................................................................................................................................... 27 I/O SPACE REGISTERS................................................................................................................................................................. 28 Floppy Disk Controller I/O Registers............................................
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Technologies, Inc. VT1211 LPC SuperIO and Hardware Monitor We Connect LIST OF FIGURES FIGURE 1. FIGURE 2. FIGURE 3. FIGURE 4. VT1211 PIN DIAGRAM (TOP VIEW)...................................................................................................................... 4 LPC INTERFACE BLOCK DIAGRAM ................................................................................................................... 6 REGISTER MAP .........................................................................
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Technologies, Inc. VT1211 LPC SuperIO and Hardware Monitor We Connect • Floppy Disk Controller – – – • Game Port – – • Input mode supports switch de-bounce Output mode supports one set of programmable LED blinking periods Watch Dog Timer – – • UART implementation Supports direct connect to MPU-401 MIDI 56 General Purpose I/O Pins – – • Built-in 558 quad timers and buffer chips Supports direct connection to two joysticks Dedicated MIDI Interface – – • Supports two 360K / 720K / 1.2M / 1.
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Technologies, Inc. VT1211 LPC SuperIO and Hardware Monitor We Connect OVERVIEW The VT1211 is a full function Super I/O chip that provides the most commonly used legacy Super I/O functionality plus the latest Hardware monitor initiatives. The device uses an LPC interface that complies with “LPC Interface Specification Revision 1.0”.
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Technologies, Inc. VT1211 LPC SuperIO and Hardware Monitor We Connect Pin List Table 1.
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Technologies, Inc. VT1211 LPC SuperIO and Hardware Monitor We Connect Pin Descriptions Table 2. Pin Descriptions LPC BUS INTERFACE Signal Name Pin # Type LRESET# LFRAME# LAD[3:0] LDRQ# 28 27 23-26 20 I O I I 21 19 IO I SERIRQ PCICLK Description LPC Reset. LPC Frame. This signal indicates the start of an LPC cycle. LPC Address / Data 3-0. 4-bit LPC address / bidirectional data lines. LAD0 is the lsb. LPC DMA Request. An encoded signal for DMA channel select.
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Technologies, Inc. VT1211 LPC SuperIO and Hardware Monitor We Connect Floppy Disk Controller Symbol Pin # Type DRVB# DRVA# MTRA# MTRB# HDSEL# DSEL0# 4 6 3 7 15 1 O O O O O O DSEL1# / MSO / OVOLT STEP# DIR# WGATE# WDATA# RDATA# TRK0# INDEX# WPT# DSKCHG# 120 9 8 11 10 14 12 2 13 16 O O O O O I I I I I Description Drive B Enable. Drive A Enable. Motor A Enable. Motor B Enable Side 1 Select. Density Select 0.
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Technologies, Inc. VT1211 LPC SuperIO and Hardware Monitor We Connect MIDI Interface Signal Name MSI / OVFAN / WDTO MSO / OVOLT / DSEL1 Pin # Type 119 120 I O Description MIDI Input. MIDI Output. Game Port Signal Name Pin # Type JAB1 / GP10 JBB1 / GP11 JACX / GP12 JBCX / GP13 JBCY / GP14 JACY / GP15 JBB2 / GP16 JAB2 / GP17 128 127 126 125 124 123 122 121 I I I I I I I I Description Joystick A Button # 1 Input. Joystick B Button # 1 Input. Joystick A X-axis Resistor Input.
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Technologies, Inc. VT1211 LPC SuperIO and Hardware Monitor We Connect Serial Port 2 Signal Name Pin # Type CTS2# / VID4 / GP77 DSR2# / VID3 / GP76 RTS2# / VID2 / GP75 55 I I IO I I IO O O IO DTR2# / VID1 / GP74 58 O I IO SIN2# / VID0 / GP73 SOUT2# / SMBCK / GP72 DCD2# / SMBDT / GP71 RI2# / GP70 / ITMOFF / SCLK 59 I I IO O IO IO I IO IO I IO 56 57 61 62 63 Description Clear To Send. The default function of this pin is Clear To Send. Low indicates that the modem is ready to accept data.
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Technologies, Inc. VT1211 LPC SuperIO and Hardware Monitor We Connect General Purpose I/O Group 1 Signal Name Pin # Type GP10 / JAB1 GP11 / JBB1 GP12 / JACX GP13 / JBCX GP14 / JBCY GP15 / JACY GP16 / JBB2 GP17 / JAB2 128 127 126 125 124 123 122 121 IO IO IO IO IO IO IO IO Description General Purpose I/O 10. General Purpose I/O 11. General Purpose I/O 12. General Purpose I/O 13. General Purpose I/O 14. General Purpose I/O 15. General Purpose I/O 16. General Purpose I/O 17.
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Technologies, Inc. VT1211 LPC SuperIO and Hardware Monitor We Connect General Purpose I/O Group 4 Signal Name Pin # Type GP40 / XA0 GP41 / XA1 GP42 / XA2 GP43 / XA3 GP44 / XA4 GP45 / XA5 GP46 / XA6 GP47 / XA7 85 84 83 82 81 80 79 78 IO IO IO IO IO IO IO IO Description General Purpose I/O 40. General Purpose I/O 41. General Purpose I/O 42. General Purpose I/O 43. General Purpose I/O 44. General Purpose I/O 45. General Purpose I/O 46. General Purpose I/O 47.
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Technologies, Inc. VT1211 LPC SuperIO and Hardware Monitor We Connect Hardware Monitor Signal Name Pin # Type Description 103, 104, 107-109 106 I Universal Input Channels 1–5. 0 to 2.60 V FSR Analog Inputs. O DTDP DTDN VID0 / GP73 / SIN2 VID1 / GP74 / DTR2# VID2 / GP75 / RTS2# VID3 / GP76 / DSR2# VID4 / GP77 / CTS2# COPEN / OVFAN / GP23 / ATEST OVTEMP# OVFAN / WDTO / MSI OVOLT / DSEL1 / MSO BEEP 111 110 59 I I I 58 I 57 I 56 I 55 I 101 IO Reference Voltage Output.
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Technologies, Inc. VT1211 LPC SuperIO and Hardware Monitor We Connect Flash ROM Interface Signal Name Pin # Type XA[18-16] / GP[62-60], XA[15-8] / GP[57-50], XA[7-0] / GP[47-40] 66-68, 69-74, 76-77, 78-85 86-89, 91-94 O ROM Address[18:0]. The default function of these pins is for flash ROM address input. The function of these pins decided by the GPIO configuration register. IO ROM Data[7:0]. The default function of these pins is for flash ROM data input.
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Technologies, Inc. VT1211 LPC SuperIO and Hardware Monitor We Connect REGISTERS Register Overview Configuration Sequence The following tables summarize the configuration and I/O registers of the VT1211. These tables also document the power-on default value (“Default”) and access type (“Acc”) for each register. Access type definitions used are RW (Read/Write), RO (Read/Only), “—” for reserved / used (essentially the same as RO), and RWC (or just WC) (Read / Write 1’s to Clear individual bits).
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Technologies, Inc. VT1211 LPC SuperIO and Hardware Monitor We Connect I/O Port 2Eh or 4Eh Index Floppy Disk I/O Regs Offset 2 - Command Offset 4 - Status / Rate Select Offset 5 - Data Offset 7 - Disk Change Status Parallel Port I/O Regs Offset 0 - Data Offset 1 - Status Offset 2 - Control Offset 3 - ... Serial Port 1 I/O Regs Offset 0 - Tx / Rx Buffer Offset 1 - Interrupt Enable Offset 2 - Interrupt Status Offset 3 - Control Offset 4 - ...
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Technologies, Inc. VT1211 LPC SuperIO and Hardware Monitor We Connect Register Summary Tables Table 3. Register Summary – Configuration Index Table 4.
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Technologies, Inc. VT1211 LPC SuperIO and Hardware Monitor We Connect Table 5.
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Technologies, Inc. VT1211 LPC SuperIO and Hardware Monitor We Connect Table 6.
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Technologies, Inc. VT1211 LPC SuperIO and Hardware Monitor We Connect Hardware Monitor I/O Space Registers Offset Base = LDN B Rx61-60 (EC00h) Default Acc 10 SELD0 [7:0] For AFE as Digital filter 00 RW parameter SELD [7:0] 11 SELD1[7:0] for as SELD[15:8] 00 RW 12 SELD2[7:0] for as SELD[19:16] 00 RW 13 Analog data D[15:8] 00 RW 14 Analog data D[7:0] 00 RW 15 Digital data D[7:0] 00 RW 16 Channel Counter 00 RW 17 Data Valid & Channel Indications.
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Technologies, Inc. VT1211 LPC SuperIO and Hardware Monitor We Connect Register Descriptions Chip (Global) Control Registers Offset 07 - Logical Device Number..................................RW 7-0 Logical Device Number ....................... default = 00h This register selects the current logical device. Offset 20 - Device ID..........................................................RO 7-0 Device ID ..............................................default = 3Ch Offset 21 - Device Revision..................
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Technologies, Inc. VT1211 LPC SuperIO and Hardware Monitor We Connect Offset 26 - GPIO Port 7 Pin Select ..................................RW 7 Pin 55 0 CTS2# ...................................................default 1 GP77 6 Pin 56 0 DSR2# ...................................................default 1 GP76 5 Pin 57 0 RTS2# ...................................................default 1 GP75 4 Pin 58 0 DTR2# ..................................................default 1 GP74 3 Pin 59 0 SIN2 ....................
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Technologies, Inc. VT1211 LPC SuperIO and Hardware Monitor We Connect Floppy Disk Controller Registers (LDN 0) Offset 30 – Floppy Controller Activate...........................RW 7-1 Reserved ........................................ always reads 0 0 Floppy Disk Controller Enable.................. default = 0 Offset 60 – Floppy Controller Base Address (FCh) .......RW 7-1 ADR9 ~ ADR3..................... always reads 1111 110b 0 Must be 0 ..............................................
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Technologies, Inc. VT1211 LPC SuperIO and Hardware Monitor We Connect Parallel Port Registers (LDN 1) Offset 30 – Parallel Port Activate (03h) ..........................RW 7-2 Reserved ........................................ always reads 0 1-0 Parallel Port Enable….…… ............... default = 11b 00 SPP Mode 01 ECP Mode 10 EPP Mode 11 PIO Disable Offset 60 – Parallel Port Base Address (DEh)................RW 7-0 ADR9 ~ ADR2...................................
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Technologies, Inc. VT1211 LPC SuperIO and Hardware Monitor We Connect Serial Port 1 Registers (LDN 2) Serial Port 2 Registers (LDN 3) Offset 30 – Serial Port 1 Activate ....................................RW 7-1 Reserved ........................................ always reads 0 0 Serial Port 1 Function 0 Disable ...................................................default 1 Enable Offset 30 – Serial Port 2 Activate................................... RW 7-1 Reserved ........................................
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Technologies, Inc. VT1211 LPC SuperIO and Hardware Monitor We Connect MIDI Registers (LDN 6) GPIO Registers (LDN 8) Offset 30 – MIDI Activate (00h) ......................................RW 7-1 Reserved ........................................ always reads 0 0 MIDI Function 0 Disable ...................................................default 1 Enable Offset 30 – GPIO Activate (00h) ..................................... RW 7-1 Reserved ........................................
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Technologies, Inc. VT1211 LPC SuperIO and Hardware Monitor We Connect Watch Dog Registers (LDN 9) FIR Registers (LDN C) Offset 30 – Watch Dog Activate (00h).............................RW 7-1 Reserved .............................................. default = 0 0 Watch Dog Function….……................... default = 0 0 Disable ...................................................default 1 Enable Offset 30 – Fast IR Activate (00h)................................... RW 7-1 Reserved ..........................
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Technologies, Inc. VT1211 LPC SuperIO and Hardware Monitor We Connect I/O Space Registers Floppy Disk Controller I/O Registers These registers are normally accessed at standard FDC I/O port addresses 3F0-3F7h (see LDN 0 Rx61-60 for the FDC Port I/O Base setting). Offset 2 – FDC Command................................................
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Technologies, Inc. VT1211 LPC SuperIO and Hardware Monitor We Connect Parallel Port I/O Registers These registers are normally accessed at standard Parallel Port I/O addresses 378-37Fh (see LDN 1 Rx61-60 for the Parallel Port I/O Base setting). Offset 0 – Parallel Port Data ............................................RW 7-0 Parallel Port Data Offset 1 – Parallel Port Status...........................................
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Technologies, Inc. VT1211 LPC SuperIO and Hardware Monitor We Connect Serial Port 1 I/O Registers These registers are normally accessed at standard Parallel Port I/O addresses 3F8-3FFh (see LDN 1 Rx61-60 for the Parallel Port I/O Base setting). Offset 0 – Transmit / Receive Buffer...............................RW 7-0 Serial Data Offset 1 – Interrupt Enable..............................................RW 7-4 Undefined ..........................................
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Technologies, Inc. VT1211 LPC SuperIO and Hardware Monitor We Connect Revision 1.
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Technologies, Inc. VT1211 LPC SuperIO and Hardware Monitor We Connect Serial Port 2 I/O Registers These registers are normally accessed at standard Parallel Port I/O addresses 2F8-2FFh (see LDN 1 Rx61-60 for the Parallel Port I/O Base setting). Offset 0 – Transmit / Receive Buffer...............................RW 7-0 Serial Data Port COM2Base+1 – Interrupt Enable...........................RW 7-4 Undefined ..........................................
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Technologies, Inc. VT1211 LPC SuperIO and Hardware Monitor We Connect Revision 1.
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Technologies, Inc. VT1211 LPC SuperIO and Hardware Monitor We Connect MIDI I/O Registers Game Port I/O Registers These registers are accessed at I/O port addresses offset from the MIDI I/O Base address (“Plug and Play” programmable via LDN 6 Rx61-60).
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Technologies, Inc. VT1211 LPC SuperIO and Hardware Monitor We Connect GPIO I/O Registers These registers are normally accessed at I/O port addresses starting at E900h (see LDN 8 Rx61-60 for the GPIO I/O Port Base setting). Offset 00 – GPIO Port 1 Data ..........................................RW 7-0 GPIO 1x Data.......................................
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Technologies, Inc. VT1211 LPC SuperIO and Hardware Monitor We Connect Offset 05 – GPIO Events Status A................................ RWC 7-0 GPx [7:0] Event Status A This register shows event detection status of either GP1X or GP3X, according to Global Register Rx28[6]. These bits are only set by hardware and can only be reset by writing a 1 to relative bit position. 0 Event undetected....................................default 1 Event detected Offset 06 – GPIO Events Enable A .........................
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Technologies, Inc. VT1211 LPC SuperIO and Hardware Monitor We Connect Watch Dog I/0 Registers These registers are normally accessed at I/O port addresses starting at EA00h (see LDN 9 Rx61-60 for the Watch Dog I/O Port Base setting). Offset 00 – Watch Dog Status 0 (01h) ..............................RO 7-1 Reserved….…… ................................ always reads 0 0 Watch Dog Time Out (WDTO) ..........................
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Technologies, Inc. VT1211 LPC SuperIO and Hardware Monitor We Connect Wake-Up Control I/0 Registers These registers are normally accessed at I/O port addresses starting at EB00h (see LDN A Rx61-60 for the Wake Up Control I/O Port Base setting). Offset 00 –Wake-Up Status........................................... RWC 7 Module IRQ Status 0 Event not active .....................................default 1 Event active This bit is only set by hardware and can only be reset by writing a 1 to this bit position.
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Technologies, Inc. VT1211 LPC SuperIO and Hardware Monitor We Connect Offset 08 – GPIO Port 0 Data ..........................................RW 7-0 GPIO Data 0......................................... default = 00h If this register as GPO, it should be program with the value of each bit determines the value drive on the corresponding GPIO pin when its output buffer is enabled. Writing to the bit latches the written data. Reading the bit returns its value, regardless of the pin value.
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Technologies, Inc. VT1211 LPC SuperIO and Hardware Monitor We Connect Offset 0E – SMI# Event Enable 0....................................RW 7 Module IRQ 0 Disable ...................................................default 1 Enable 6 Software Enable 0 Disable ...................................................default 1 Enable 5-3 Reserved ........................................ always reads 0 2 RI2# Enable 0 Disable ...................................................
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Technologies, Inc. VT1211 LPC SuperIO and Hardware Monitor We Connect Offset 1C – Event Configuration .....................................RW 7 GPIO Event Source Select 0 Select GPIO2x as event input source.....default 1 Select GPIO7x as event input source 6 Reserved ........................................ always reads 0 5 SMI# Output Select 0 Wake-up events that are enabled active the SMI# signal control by SMIENx register and regardless of the WUENx register .........
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Technologies, Inc. VT1211 LPC SuperIO and Hardware Monitor We Connect Hardware Monitor I/0 Registers These registers are normally accessed at I/O port addresses starting at EC00h (see LDN B Rx61-60 for the Hardware Monitor I/O Port Base setting). Offset 10 –SELD0 [7:0] for AFE as Digital filter parameter SELD [7:0] .....................................................RW Offset 1D –Hot Temp Limit (H) (For Temp reading 3) RW Offset 1E–Hot Temp Hysteresis Limit (Low) ................
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Technologies, Inc. VT1211 LPC SuperIO and Hardware Monitor We Connect Offset 2B – UCH2 High Limit..........................................RW Offset 3D – UCH1 High Limit (Default for Temperature Reading 2) ......................................................................... RW Offset 2C – UCH2 Low Limit ..........................................RW Offset 3E – UCH1 Low Limit.......................................... RW Offset 2D – UCH3 High Limit .........................................
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Technologies, Inc. VT1211 LPC SuperIO and Hardware Monitor We Connect Offset 40 – Configuration (08h).......................................RW 7 Initialization 0 Power-on default....................................default 1 Restore powerup default values to the Configuration register, Interrupt Status register, Interrupt Mask registers, Fan Divisor / RST# / OS# register, and OS# Configuration / Temperature resolution register. This bit automatically clears itself. 6 CI Pulse .............................
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Technologies, Inc. VT1211 LPC SuperIO and Hardware Monitor We Connect Offset 43 – Interrupt Mask 1 ...........................................RW 7 FAN2 .............................................. default = 0 A one disables the corresponding interrupt status bit for the INT interrupt. 6 FAN1 .............................................. default = 0 A one disables the corresponding interrupt status bit for the INT interrupt. 5 Over Temp 1(Intel Thermal TIN0) .......
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Technologies, Inc. VT1211 LPC SuperIO and Hardware Monitor We Connect Offset 47 – Fan Speed Control (25h) ..............................RW 7-6 FAN2 RPM Control FAN2 Speed Control 00 Divide by 1 01 Divide by 2.............................................default 10 Divide by 4 11 Divide by 8 5-4 FAN1 RPM Control FAN1 Speed Control 00 Divide by 1 01 Divide by 2.............................................default 10 Divide by 4 11 Divide by 8 3-0 Reserved ........................................
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Technologies, Inc. VT1211 LPC SuperIO and Hardware Monitor We Connect Offset 4B – Temperature Configuration 1 (15h)............RW 7-6 Temperature 1….................................................. RO For thermal input 1:10- bit temperature resolution. (LSB temp1 [1:0]). 5-4 Same as Bits 1-0 But For Internal Thermal Input 3 Same as above bit 1 & 0, but for thermal input 3 (Reserved for internal thermal diode).......... def = 01b 3 Hot Temperature Interrupt mode select Bit 1 of Thermal Input of UCH1………..
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Technologies, Inc. VT1211 LPC SuperIO and Hardware Monitor We Connect 1 Offset 4C – Temperature Configuration 2 (55h) ...........RW 7-6 Same as bit 1-0 but for Thermal input of UCH5 .......................................... default = 00b Same as above bit 1 & 0,but for Thermal input of UCH5 5-4 Same as bit 1-0 but for Thermal input of UCH4 ..........................................
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Technologies, Inc. VT1211 LPC SuperIO and Hardware Monitor We Connect Offset 4D – Temperature Resolution ...............................RO 7-6 Temp of UCH5 For thermal input of UCH5: 10-bit temperature resolution (LSB TEMP [1:0]). 5-4 Temp of UCH4 For thermal input of UCH4: 10-bit temperature resolution (LSB TEMP [1:0]). 3-2 Temp of UCH3 For thermal input of UCH3: 10-bit temperature resolution (LSB TEMP [1:0]). 1-0 Temp of UCH2 For thermal input of UCH2: 10-bit temperature resolution (LSB TEMP [1:0]).
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Technologies, Inc. VT1211 LPC SuperIO and Hardware Monitor We Connect Offset 50 – PWM Clock Selection (00h)..........................RW 7-3 Reserved ........................................ always reads 0 2-0 PWM Clock Selection........................ default = 000b 000 90K Hz 001 45K Hz 010 22.5K Hz 011 11.25K Hz 100 5.63K Hz 101 2.8K Hz 110 1.4K Hz 111 700 Hz Offset 51 – PWM Control (00h).......................................RW 7 Reserved ........................................
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Technologies, Inc. VT1211 LPC SuperIO and Hardware Monitor We Connect IrDA (VFIR) Host Controller I/0 Registers These registers are normally accessed at I/O port addresses starting at E800h (see LDN C Rx61-60 for the VFIR Controller I/O Port Base setting). Offset 10 – Infrared Configuration Low 0......................RW 7 CRC Length 0 32-bit CRC.............................................default 1 16-bit CRC 6 FIR Mode 0 Disable ...................................................
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Technologies, Inc. VT1211 LPC SuperIO and Hardware Monitor We Connect Offset 12 – Infrared SIR BOF (C0h)...............................RW 7-0 BOF Flag.............................................default = C0h Value used as Begin-of-Flag for SIR format. Offset 13 – Infrared SIR EOF (C1h)...............................RW 7-0 EOF Flag.............................................default = C1h Value used as of End-of-Flag for SIR format. Offset 14 – Infrared Status High 0 ..................................
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Technologies, Inc. VT1211 LPC SuperIO and Hardware Monitor We Connect Offset 1E – Infrared Configuration 3 (00h)....................RW 7-6 Filter Select 00 Highest filter ..........................................default 01 Medium high filter 10 Medium low filter 11 Lowest filter 5 FIR Adjacent Pulse Width Packet Circuit 0 Enable ....................................................default 1 Disable 4 FIR Pulse Width Adjustment. 0 Enable ....................................................
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Technologies, Inc. VT1211 LPC SuperIO and Hardware Monitor We Connect Offset 21 – Host Status (00h) ............................................RO 7 Reserved ........................................ always reads 0 6 Timer Interrupt ................................................... RO ‘1’ indicates that a timer interrupt is pending. 5 Tx Interrupt ......................................................... RO ‘1’ indicates that a transmitter interrupt is pending. 4 Rx Interrupt ...........................
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Technologies, Inc. VT1211 LPC SuperIO and Hardware Monitor We Connect Offset 24 – Tx Control 2 (40h) .........................................RW 7 Force Underrun 0 Disable ...................................................default 1 Enable an underrun on this packet for testing (for an underrun occur, the Tx count should be greater than 18 bytes) 6 Transmit CRC 0 Setting for SIR mode or bridging application where CRC should not be generated by hardware 1 Enable Tx CRC for synchronous packets ...
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Technologies, Inc. VT1211 LPC SuperIO and Hardware Monitor We Connect Offset 26 – Rx Control (40h)............................................RW 7-6 RxFIFO Level An interrupt occurs when bit-1 (Rx FIFO Ready Interrupt) is set and the Receive FIFO level reaches the following setting (settings depend on FIFO Size bits 1-0): 00 Full level ................................................
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Technologies, Inc. VT1211 LPC SuperIO and Hardware Monitor We Connect Offset 28 – Reset Command (00h)...................................RW 7-4 Reset Command [3:0].........................................WO Used to send a reset signal to the appropriate hardware in order to clear a particular status condition, a counter , or general reset. These bits are self-clearing (i.e., the programmer does not need to reset the Reset Command bit value to 0000). 0000 No reset command .................................
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Technologies, Inc. VT1211 LPC SuperIO and Hardware Monitor We Connect Offset 32 – General Purpose Timer.................................RW 7-0 Timer .............................................. default = 0 The current value of the up-counter is returned when host reading this register. The running value is reset to ‘0’ if host write to this register. The up-counter has a count time of 125us per increment. The counter will stop incrementing when it reaches the programmed target value.
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Technologies, Inc. VT1211 LPC SuperIO and Hardware Monitor We Connect ELECTRICAL SPECIFICATIONS Table 8. Absolute Maximum Ratings Symbol Parameter TSTG Storage temperature Min Max Unit –55 125 oC 0 55 oC TC Case operating temperature VCC Power supply voltages –0.5 4.0 Volts VI Input voltage –0.5 5.5 Volts VO Output voltage at any output –0.5 VCC + 0.
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Technologies, Inc. VT1211 LPC SuperIO and Hardware Monitor We Connect MECHANICAL SPECIFICATIONS D D1 D2 A A2 103 A1 0.05 s 65 102 -D64 -B- E E1 E2 -A- 128 38 4X e b D 4X D 39 1 aaa C A-B D c bbb H A-B D ddd M C A-B s D s SEE DETAIL "F" 0- 1 0 D -C- SEATING PLANE CONTROL DIMENSIONS ARE IN MILLIMETERS. MILLIMETER INCH SYMBOL MIN. NOM. MAX. MIN. NOM. MAX. 0.063 1.60 A 0.006 0.05 0.15 0.002 A1 1.35 1.40 1.45 0.053 0.055 0.057 A2 22.00 BSC. 0.866 BSC. D 20.00 BSC. 0.787 BSC. D1 16.