Product specifications

VT8235 V-Link South Bridge
Revision 1.22 October 24, 2002 -93- Device 17 Function 1 Enhanced IDE Controller Registers
Device 17 Function 1 Registers - Enhanced IDE Controller
This Enhanced IDE controller interface is fully compatible
with the SFF 8038i v.1.0 specification. There are two sets of
software accessible registers -- PCI configuration registers and
Bus Master IDE I/O registers. The PCI configuration registers
are located in the function 1 PCI configuration space of the
VT8235. The Bus Master IDE I/O registers are defined in the
SFF8038i v1.0 specification.
PCI Configuration Space Header
Offset 1-0 - Vendor ID (1106h=VIA)............................... RO
Offset 3-2 - Device ID (0571h=IDE Controller).............. RO
Offset 5-4 – Command (0000h) ........................................RW
15-3 Reserved ........................................ always reads 0
2 Bus Master ............................. default = 0 (disabled)
S/G operation can be issued only when the “Bus
Master” bit is enabled.
1 Reserved ........................................ always reads 0
0 I/O Space ............................. default = 0 (disabled)
When the “I/O Space” bit is disabled, the device will
not respond to any I/O addresses for both compatible
and native mode.
Offset 7-6 – Status (0290h)) .............................................. RO
15 Detected Parity Error................................ fixed at 0
14 Signalled System Error.............................. fixed at 0
13 Received Master Abort............................ default = 0
12 Received Target Abort............................. default = 0
11 Signalled Target Abort.............................. fixed at 0
10-9 DEVSEL# Timing.......... always reads 01 (medium)
8 Data Parity Detected.................................. fixed at 0
7 Fast Back to Back....................................... fixed at 1
6-5 Reserved ........................................ always reads 0
4 Capability List............................................ fixed at 1
3-0 Reserved ........................................ always reads 0
Offset 8 - Revision ID (06) ................................................ RO
7-0 Revision Code for IDE Controller Logic Block
Offset 9 - Programming Interface................................... RW
7 Master IDE Capability...........fixed at 1 (Supported)
6-4 Reserved ........................................always reads 0
3 Programmable Indicator - Secondary...... fixed at 1
Supports both modes (may be set to either mode by
writing Rx42[6])
2 Channel Operating Mode - Secondary
0 Compatibility Mode............................... default
1 Native Mode
1 Programmable Indicator - Primary.......... fixed at 1
Supports both modes (may be set to either mode by
writing Rx42[7])
0 Channel Operating Mode - Primary
0 Compatibility Mode............................... default
1 Native Mode
Compatibility Mode (fixed IRQs and I/O addresses):
Command Block Control Block
Channel
Registers Registers IRQ
Pri 1F0-1F7 3F6 14
Sec 170-177 376 15
Native PCI Mode (registers are programmable in I/O space)
Command Block Control Block
Channel
Registers Registers
Pri BA @offset 10h BA @offset 14h
Sec BA @offset 18h BA @offset 1Ch
Command register blocks are 8 bytes of I/O space
Control registers are 4 bytes of I/O space (only byte 2 is used)
Offset A - Sub Class Code (01h=IDE Controller)...........RO
Offset B - Base Class Code (01h=Mass Storage Ctrlr) ...RO