Product specifications

VT8235 V-Link South Bridge
Revision 1.22 October 24, 2002 -90- I/O Space System Management Bus Registers
System Management Bus I/O-Space Registers
The base address for these registers is defined in RxD1-D0 of
the Device 17 Function 0 PCI configuration registers. The
System Management Bus I/O space is enabled for access by
the system if Device 17 Function 0 RxD2[0] = 1.
I/O Offset 00 – SMBus Host Status...............................RWC
7 Reserved ........................................ always reads 0
6 SMB Semaphore...............................................RWC
This bit is used as a semaphore among various
independent software threads that may need to use
the Host SMBus logic and has no effect on hardware.
After reset, this bit reads 0. Writing 1 to this bit
causes the next read to return 0, then all reads after
that return 1. Writing 0 to this bit has no effect.
Software can therefore write 1 to request control and
if readback is 0 then it will own usage of the host
controller.
5 Reserved ........................................ always reads 0
4 Failed Bus Transaction....................................RWC
0 SMBus interrupt not caused by failed bus
transaction ............................................. default
1 SMBus interrupt caused by failed bus
transaction. This bit may be set when the
KILL bit (I/O Rx02[1]) is set and can be
cleared by writing a 1 to this bit position.
3 Bus Collision.....................................................RWC
0 SMBus interrupt not caused by transaction
collision................................................. default
1 SMBus interrupt caused by transaction
collision. This bit is only set by hardware and
can be cleared by writing a 1 to this bit
position.
2 Device Error.....................................................RWC
0 SMBus interrupt not caused by generation of
an SMBus transaction error................... default
1 SMBus interrupt caused by generation of an
SMBus transaction error (illegal command
field, unclaimed host-initiated cycle, or host
device timeout). This bit is only set by
hardware and can be cleared by writing a 1 to
this bit position.
1 SMBus Interrupt..............................................RWC
0 SMBus interrupt not caused by host command
completion............................................. default
1 SMBus interrupt caused by host command
completion. This bit is only set by hardware
and can be cleared by writing a 1 to this bit
position.
0 Host Busy ......................................................... RO
0 SMBus controller host interface is not
processing a command .......................... default
1 SMBus host controller is busy processing a
command. None of the other SMBus registers
should be accessed if this bit is set.
I/O Offset 01h – SMBus Slave Status........................... RWC
7-6 Reserved ........................................always reads 0
5 Alert Status ..................................................... RWC
0 SMBus interrupt not caused by SMBALERT#
signal ....................................................default
1 SMBus interrupt caused by SMBALERT#
signal. This bit will be set only if the Alert
Enable bit is set in the SMBus Slave Control
Register at I/O Offset R08[3]. This bit is only
set by hardware and can be cleared by writing
a 1 to this bit position.
4 Shadow 2 Status............................................... RWC
0 SMBus interrupt not caused by address match
to SMBus Shadow Address Port 2.........default
1 SMBus interrupt or resume event caused by
slave cycle address match to SMBus Shadow
Address Port 2. This bit is only set by
hardware and can be cleared by writing a 1 to
this bit position.
3 Shadow 1 Status............................................... RWC
0 SMBus interrupt not caused by address match
to SMBus Shadow Address Port 1.........default
1 SMBus interrupt or resume event caused by
slave cycle address match to SMBus Shadow
Address Port 1. This bit is only set by
hardware and can be cleared by writing a 1 to
this bit position.
2 Slave Status ..................................................... RWC
0 SMBus interrupt not caused by slave event
match ....................................................default
1 SMBus interrupt or resume event caused by
slave cycle event match of the SMBus Slave
Command Register at PCI Function 4
Configuration Offset D3h (command match)
and the SMBus Slave Event Register at
SMBus Base + Offset 0Ah (data event match).
This bit is only set by hardware and can be
cleared by writing a 1 to this bit position.
1 Reserved ........................................always reads 0
0 Slave Busy .........................................................RO
0 SMBus controller slave interface is not
processing data ......................................default
1 SMBus controller slave interface is busy
receiving data. None of the other SMBus
registers should be accessed if this bit is set.