Product specifications

VT8235 V-Link South Bridge
Revision 1.22 October 24, 2002 -89- I/O Space Power Management Registers
General Purpose I/O Registers
I/O Offset 45 – SMI / IRQ / Resume Status .................... RO
7-5 Reserved ........................................ always reads 0
4 Latest PCSn Status
0 Latest PCSn was an I/O Read
1 Latest PCSn was an I/O Write
3 Serial SMI Status
This bit is used to report a Serial-IRQ-generated SMI.
2 Reserved ........................................ always reads 0
1 SMBus IRQ Status
This bit is used to report an SMBus SMI.
0 SMBus Resume Status
This bit is used to report an SMBus Resume Event.
I/O Offset 4B-48 - GPI Port Input Value (GPIVAL) ..... RO
31-0 GPI[31-0] Input Value............................. Read Only
I/O Offset 4F-4C - GPO Port Output Value (GPOVAL)RW
Reads from this register return the last value written (held on
chip). Some GPIO pins can be used as both input and output
(GPIO pins 8-15 and 20-31). The output type of these pins is
OD (open drain) so to use one of these pins as an input pin, a
one must be written to the corresponding bit of this register.
See also Function 0 RxE4[4-3] for I/O control of GPIO pins 8-
15.
31-0 GPO[31-0] Output Value..............def = FFFFFFFFh
I/O Offset 50 – GPI Pin Change Status ...........................RW
7 GPI27 Pin Change Status........................ default = 0
6 GPI26 Pin Change Status........................ default = 0
5 GPI25 Pin Change Status........................ default = 0
4 GPI24 Pin Change Status........................ default = 0
3 GPI19 Pin Change Status........................ default = 0
2 GPI18 Pin Change Status........................ default = 0
1 GPI17 Pin Change Status........................ default = 0
0 GPI16 Pin Change Status........................ default = 0
I/O Offset 52 – GPI Pin Change SCI/SMI Select............RW
7 GPI27 Pin SCI / SMI Select
6 GPI26 Pin SCI / SMI Select
5 GPI25 Pin SCI / SMI Select
4 GPI24 Pin SCI / SMI Select
3 GPI19 Pin SCI / SMI Select
2 GPI18 Pin SCI / SMI Select
1 GPI17 Pin SCI / SMI Select
0 GPI16 Pin SCI / SMI Select
0 SCI on pin input change........................ default
1 SMI on pin input change
I/O Trap Registers
I/O Offset 57-54 – I/O Trap PCI Data .............................RO
31-0 PCI Data During I/O Trap SMI
I/O Offset 59-58 – I/O Trap PCI I/O Address.................RO
15-0 PCI Address During I/O Trap SMI
I/O Offset 5A – I/O Trap PCI Command / Byte Enable RO
7-4 PCI Command Type During I/O Trap SMI
3-0 PCI Byte Enable During I/O Trap SMI
I/O Offset 5C – CPU Performance Control.................... RW
7-2 Reserved ........................................always reads 0
1 Lower CPU Voltage During C3 / S1
This bit controls the CPU voltage in C3/S1 state. The
voltage is lowered using the VGATE signal (PMIO
RxE5[4] must be 0 to enable the voltage change
function).
0 Disable (normal voltage during C3/S1).......def
1 Enable (lower voltage during C3/S1)
0 Lower CPU Frequency During C3 / S1
This bit controls the CPU frequency in C3/S1 state.
The frequency is lowered using the GHI# signal
(PMIO RxE5[3] must be 0 to enable the frequency
change function).
0 Disable (normal frequency during C3/S1)...def
1 Enable (lower frequency during C3/S1)