Product specifications

VT8235 V-Link South Bridge
Revision 1.22 October 24, 2002 -88- I/O Space Power Management Registers
I/O Offset 3B-38 - GP Timer Reload Enable ..................RW
All bits in this register default to 0 on power up.
31-8 Reserved ........................................ always reads 0
7 GP1
Timer Reload on KBC Access
0 Normal GP1 Timer Operation............... default
1 Setting of KBC_STS causes the GP1 timer to
reload.
6 GP1
Timer Reload on Serial Port Access
0 Normal GP1 Timer Operation .............. default
1 Setting of COMA_STS or COMB_STS causes
the GP1 timer to reload.
5 Reserved ........................................ always reads 0
4 GP1
Timer Reload on VGA Access
0 Normal GP1 Timer Operation .............. default
1 Setting of VGA_STS causes the GP1 timer to
reload.
3 GP1
Timer Reload on IDE/Floppy Access
0 Normal GP1 Timer Operation .............. default
1 Setting of FDC_STS, SIDE_STS, or
PIDE_STS causes the GP1 timer to reload.
2 GP3
Timer Reload on GPIO Range 1 Access
0 Normal GP3 Timer Operation .............. default
1 Setting of GR1_STS causes the GP3 timer to
reload.
1 GP2
Timer Reload on GPIO Range 0 Access
0 Normal GP2 Timer Operation .............. default
1 Setting of GR0_STS causes the GP2 timer to
reload.
0 GP0
Timer Reload on Primary Activity
0 Normal GP0 Timer Operation .............. default
1 Setting of PACT_STS causes the GP0 timer to
reload. Primary activities are enabled via the
Primary Activity Detect Enable register (offset
37-34) with status recorded in the Primary
Activity Detect Status register (offset 33-30).
I/O Offset 40 – Extended I/O Trap Status................... RWC
7-5 Reserved ........................................always reads 0
4 BIOS Write Access Status
3 GP3 Timer Second Timeout With No Cycles
0 Disable...................................................default
1 Enable (GP3 timer timed out twice with no
cycles in between)
2 GP3 Timer Second Timeout Status
1 GPIO Range 3 Access Status
0 GPIO Range 2 Access Status
I/O Offset 42 – Extended I/O Trap Enable..................... RW
7-5 Reserved ........................................always reads 0
4 SMI on BIOS Write Access
This bit controls whether SMI is generated when
BIOS Write Access Status Rx40[4] = 1.
0 Disable...................................................default
1 Enable (can be reset only by OCI_Reset)
3 Reserved ........................................always reads 0
2 GP3 Timer Second Timeout Reboot
This bit controls whether the system is rebooted
when the GP3 timer times out twice (Rx40[2] = 1).
0 Disable...................................................default
1 Enable
1 SMI on GPIO Range 3 Access
This bit controls whether SMI is generated when
GPIO range 3 is accessed (Rx40[1] = 1)
0 Disable...................................................default
1 Enable
0 SMI on GPIO Range 2 Access
This bit controls whether SMI is generated when
GPIO range 2 is accessed (Rx40[0] = 1)
0 Disable...................................................default
1 Enable