Product specifications

VT8235 V-Link South Bridge
Revision 1.22 October 24, 2002 -87- I/O Space Power Management Registers
I/O Offset 33-30 - Primary Activity Detect Status.......RWC
These bits correspond to the Primary Activity Detect Enable
bits in Rx37-34. If the corresponding bit is set in that register,
setting of a bit below will cause the Primary Activity Status
(PACT_STS) bit to be set (Global Status register Rx28[0]).
All bits in this register default to 0, are set by hardware only,
and may only be cleared by writing 1s to the desired bit.
31-11 Reserved ..........................................always read 0
10 Audio Access Status.............................. (AUD_STS)
Set if Audio is accessed.
9 Keyboard Controller Access Status..... (KBC_STS)
Set if the KBC is accessed via I/O port 60h.
8 VGA Access Status................................(VGA_STS)
Set if the VGA port is accessed via I/O ports 3B0-
3DFh or memory space A0000-BFFFFh.
7 Parallel Port Access Status....................(LPT_STS)
Set if the parallel port is accessed via I/O ports 278-
27Fh or 378-37Fh (LPT2 or LPT1).
6 Serial Port B Access Status .............. (COMB_STS)
Set if the serial port is accessed via I/O ports 2F8-
2FFh or 2E8-2Efh (COM2 and COM4 respectively).
5 Serial Port A Access Status .............. (COMA_STS)
Set if the serial port is accessed via I/O ports 3F8-
3FFh or 3E8-3EFh (COM1 and COM3, respectively).
4 Floppy Access Status..............................(FDC_STS)
Set if the floppy controller is accessed via I/O ports
3F0-3F5h or 3F7h.
3 Secondary IDE Access Status...............(SIDE_STS)
Set if the IDE controller is accessed via I/O ports
170-177h or 376h.
2 Primary IDE Access Status ................. (PIDE_STS)
Set if the IDE controller is accessed via I/O ports
1F0-1F7h or 3F6h.
1 Primary Interrupt Activity Status......(PIRQ_STS)
Set on the occurrence of a primary interrupt (enabled
via the "Primary Interrupt Channel" register at
Function 4 PCI configuration register offset 44h).
0 PCI Master Access Status.....................(DRQ_STS)
Set on the occurrence of PCI master activity.
Note: Setting of Primary Activity Status (PACT_STS) may be
done to enable a "Primary Activity Event": an SMI will be
generated if the Primary Activity Enable bit is set (Global
Enable register Rx2A[0]) and/or the GP0 timer will be
reloaded if the "GP0 Timer Reload on Primary Activity" bit is
set (GP Timer Reload Enable register Rx38[0]).
Note: Bits 2-9 above also correspond to bits of GP Timer
Reload Enable register Rx38: If bits are set in that register,
setting a corresponding bit in this register will cause the GP1
timer to be reloaded.
I/O Offset 37-34 - Primary Activity Detect Enable........ RW
These bits correspond to the Primary Activity Detect Status
bits in Rx33-30. Setting of any of these bits also sets the
Primary Activity Status (PACT_STS) bit (Rx28[0]) which
causes the GP0 timer to be reloaded (if the Primary Activity
GP0 Enable bit is set) or generates an SMI (if Primary
Activity Enable is set).
31-11 Reserved ......................................... always read 0
10 SMI on Audio Status.............................. (AUD_EN)
0 Don’t set PACT_STS if AUD_STS is set ....def
1 Set PACT_STS if AUD_STS is set
9 SMI on Keyboard Controller Status..... (KBC_EN)
0 Don’t set PACT_STS if KBC_STS is set.....def
1 Set PACT_STS if KBC_STS is set
8 SMI on VGA Status................................ (VGA_EN)
0 Don’t set PACT_STS if VGA_STS is set ....def
1 Set PACT_STS if VGA_STS is set
7 SMI on Parallel Port Status.................... (LPT_EN)
0 Don’t set PACT_STS if LPT_STS is set......def
1 Set PACT_STS if LPT_STS is set
6 SMI on Serial Port B Status .............. (COMB_EN)
0 Don’t set PACT_STS if COMB_STS is set.def
1 Set PACT_STS if COMB_STS is set
5 SMI on Serial Port A Status .............. (COMA_EN)
0 Don’t set PACT_STS if COMA_STS is set.def
1 Set PACT_STS if COMA_STS is set
4 SMI on Floppy Status..............................(FDC_EN)
0 Don’t set PACT_STS if FDC_STS is set.....def
1 Set PACT_STS if FDC_STS is set
3 SMI on Secondary IDE Status...............(SIDE_EN)
0 Don’t set PACT_STS if SIDE_STS is set....def
1 Set PACT_STS if SIDE_STS is set
2 SMI on PrimaryIDE Status.................. (PIDE_EN)
0 Don’t set PACT_STS if PIDE_STS is set....def
1 Set PACT_STS if PIDE_STS is set
1 SMI on Primary IRQ Status.................(PIRQ_EN)
0 Don’t set PACT_STS if PIRQ_STS is set....def
1 Set PACT_STS if PIRQ_STS is set
0 SMI on PCI Master Status.....................(DRQ_EN)
0 Don’t set PACT_STS if DRQ_STS is set ....def
1 Set PACT_STS if DRQ_STS is set