Product specifications

VT8235 V-Link South Bridge
Revision 1.22 October 24, 2002 -86- I/O Space Power Management Registers
I/O Offset 2D-2C - Global Control...................................RW
15-12 Reserved ........................................ always reads 0
11 IDE Secondary Bus Power-Off
0 Disable .................................................. default
1 Enable
10 IDE Primary Bus Power-Off
0 Disable .................................................. default
1 Enable
9 Reserved ........................................ always reads 0
8 SMI Active
0 SMI Inactive.......................................... default
1 SMI Active. If the SMI Lock bit is set, this bit
needs to be written with a 1 to clear it before
the next SMI can be generated.
7 LID Triggering Polarity
0 Rising Edge ........................................... default
1 Falling Edge
6 THRM# Triggering Polarity
0 Rising Edge ........................................... default
1 Falling Edge
5 Battery Low Resume Disable
0 Enable resume....................................... default
1 Disable resume from suspend when
BATLOW# is asserted
4-3 Reserved ........................................ always reads 0
2 Power Button Triggering Select
0 SCI/SMI generated by PWRBTN# rising edge
.................................................... default
1 SCI/SMI generated by PWRBTN# falling
edge
Set to zero to avoid the situation where the Power
Button Status bit is set to wake up the system then
reset again by PBOR Status to switch the system into
the soft-off state.
1 BIOS Release
This bit is set by legacy software to indicate release
of the SCI/SMI lock. Upon setting of this bit,
hardware automatically sets the Global Status bit.
This bit is cleared by hardware when the Global
Status bit cleared by software.
Note that if the Global Enable bit is set (Power
Management Enable register Rx2[5]), then setting
this bit causes an SCI to be generated (because
setting this bit causes the Global Status bit to be set).
0 SMI Enable
0 Disable all SMI generation.................... default
1 Enable SMI generation
I/O Offset 2F - SMI Command........................................ RW
7-0 SMI Command
Writing to this port sets the Software SMI Status bit.
Note that if the Software SMI Enable bit is set (see
Global Enable register Rx2A[6]), then an SMI is
generated.