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100

VT8235 V-Link South Bridge

Revision 1.22 October 24, 2002 -85- I/O Space Power Management Registers

Generic Power Management Registers

I/O Offset 29-28 - Global Status....................................RWC

15 GPIO Range 1 Access Status................... default = 0

14 GPIO Range 0 Access Status................... default = 0

13 GP3 Timer Timeout Status ..................... default = 0

12 GP2 Timer Timeout Status ..................... default = 0

11 SERIRQ SMI Status................................ default = 0

10 Rx5[5] Write SMI Status......................... default = 0

This bit reports whether Rx5[5] is written. If

Rx2B[3] is set to enable SMI, an SMI in generated

when this bit = 1.

9 Reserved ........................................ always reads 0

8 PCKRUN# Resume Status ...................... default = 0

This bit is set when PCI bus peripherals wake up the

system by asserting PCKRUN#

7 Primary IRQ/INIT/NMI/SMI Resume Statusdef=0

This bit is set at the occurrence of primary IRQs as

defined in Rx85-84 of PCI configuration space

6 Software SMI Status................................ default = 0

This bit is set when the SMI Command port (Rx2F)

is written.

5 BIOS Status .............................................. default = 0

This bit is set when the Global Release bit is set to

one (typically by the ACPI software to release

control of the SCI/SMI lock). When this bit is reset

(by writing a one to this bit position) the Global

Release bit is reset at the same time by hardware.

4 Legacy USB Status................................... default = 0

This bit is set when a legacy USB event occurs. This

is normally used for USB keyboards.

3 GP1 Timer Time Out Status ................... default = 0

This bit is set when the GP1 timer times out.

2 GP0 Timer Time Out Status ................... default = 0

This bit is set when the GP0 timer times out.

1 Secondary Event Timer Time Out Status...... def=0

This bit is set when the secondary event timer times

out.

0 Primary Activity Status........................... default = 0

This bit is set at the occurrence of any enabled

primary system activity (see the Primary Activity

Detect Status register at offset 30h and the Primary

Activity Detect Enable register at offset 34h). After

checking this bit, software can check the status bits in

the Primary Activity Detect Status register at offset

30h to identify the specific source of the primary

event. Note that setting this bit can be enabled to

reload the GP0 timer (see bit-0 of the GP Timer

Reload Enable register at offset 38).

Note that SMI can be generated based on the setting of any of

the above bits (see the Rx2A Global Enable register bit

descriptions in the right hand column of this page).

The bits in this register are set by hardware only and can only

be cleared by writing a one to the desired bit position.

The bits in this register are for SMI’s only while the bits in

Rx21-20 are for SMI’s and SCI’s

I/O Offset 2B-2A - Global Enable ...................................RW

15 GPIO Range 1 SMI Enable .....................default = 0

14 GPIO Range 0 SMI Enable .....................default = 0

13 GP3 Timer Timeout SMI Enable............default = 0

12 GP2 Timer Timeout SMI Enable............default = 0

11 SERIRQ SMI Enable ...............................default = 0

10 SMI on Sleep Enable Write .....................default = 0

9 Reserved ........................................always reads 0

8 PCKRUN# Resume Enable .....................default = 0