Product specifications

VT8235 V-Link South Bridge
Revision 1.22 October 24, 2002 -80- Device 17 Function 0 Power Management Registers
General Purpose I/O Control Registers
Offset E0 – GPI Inversion Control ..................................RW
7-0 GPI[27-24, 19-16] Input Inversion
0 Non-inverted input ................................ default
1 Inverted input
Offset E1 – GPI SCI / SMI Select.....................................RW
7-0 GPI[27-24, 19-16] SCI / SMI Select
When GPI[27-24,19-16] are set to enable SCI / SMI
generation (PMIO Rx52), this field determines
whether an SCI or SMI is generated.
0 SCI .................................................... default
1 SMI
Offset E4 – GPO Pin Select ..............................................RW
7 Reserved ........................................ always reads 0
6 ACSDIN2,3 / GPIO20,21 Select (Pins U2, V1)
This bit is ignored if any of RxE5 bits 1, 2, 4, or 5 = 1
0 U2 = ACSDIN2, V1 = ACSDIN3......... default
1 U2 = GPIO20, V1 = GPIO21
5 SA[19:16] / GPO[19:16] Select (AC11, AD11,
AE11, AF11)
0 SA[19:16].............................................. default
1 GPO[19:16]
4 GPIO[15:12] Direction
0 Input (pins are GPI[15:12])................... default
1 Output (pins are GPO[15:12])
3 GPIO[11:8] Direction
0 Input (pins are GPI[11:8])..................... default
1 Output (pins are GPO[11:8])
2 GNT5# / GPO7 Select (Pin P4)
REQ5# / GPI7 Select (Pin N4)
0 P4 = GPO7, N4 = GPI7......................... default
1 P4 = GNT5#, N4 = REQ5#
1 PCISTP# / GPO6 Select (Pin AF6)
0 V6 = PCISTP#....................................... default
1 V6 = GPO6
0 CPUSTP# / GPO5 Select (Pin AC7)
0 Y5 = CPUSTP#..................................... default
1 Y5 = GPO5
Offset E5 – GPIO I/O Select 1 ......................................... RW
7 Voltage Regulator Change Timer Select
0 100 usec.................................................default
1 200 usec
6 AGPBZ# Source of Bus Master Status
0 Disable...................................................default
1 Enable
5 Reserved ........................................always reads 0
4 VGATE on GPIO8 (Pin C8)
0 U2 = GPIO8...........................................default
1 U2 = VGATE (bit 1 and RxE4[6] are ignored)
3 CPU Frequency Change
0 Enable....................................................default
1 Disable
2 PCS1# on ACSDIN3 (Pin V1)
0 V1 = ACSDIN3 / GPIO21 / SLPBTN#.default
1 V1 = PCS1# (RxE4[6] ignored)
1 PCS0# on ACSDIN2 (Pin U2)
0 U2 = ACSDIN2 / GPIO20.....................default
1 U2 = PCS0# (RxE4[6] ignored)
0 IORDY / GPI19 Select (Pin AD10)
0 AD10 = IORDY.....................................default
1 AD10 = GPI19
Offset E6 – GPIO I/O Select 2 ......................................... RW
7 GPI31 / GPO31 (GPIOE) Select (Pin AC6)
0 AC6 = GPI31......................................... default
1 AC6 = GPO31 / GPIOE
6 GPI30 / GPO30 (GPIOD) Select (Pin AD6)
0 AD6 = GPI30.........................................default
1 AD6 = GPO30 / GPIOD
5-2 Reserved ........................................always reads 0
1 GPI25 / GPO25 (GPIOC) Select (Pin AE6)
0 AE6 = GPI25 .........................................default
1 AE6 = GPO25 / GPIOC
0 GPI24 / GPO24 (GPIOA) Select (Pin AE5)
0 AE5 = GPI24 .........................................default
1 AE5 = GPO24 / GPIOA
Offset E7 – GPO Output Type.........................................RW
These bits determine whether the indicated GPO pin is open
drain or TTL when the corresponding bit of RxE6 = 1.
7 GPO31 OD/TTL Select (Pin AC6)
6 GPO30 OD/TTL Select (Pin AD6)
5-2 Reserved ........................................always reads 0
1 GPO25 OD/TTL Select (Pin AE6)
0 GPO24 OD/TTL Select (Pin AE5)
For all defined bits above:
0 OD ....................................................default
1 TTL