Product specifications

VT8235 V-Link South Bridge
Revision 1.22 October 24, 2002 -77- Device 17 Function 0 Power Management Registers
Offset 94 – Power Well Control ...................................... WO
7 SMBus Clock Select
0 SMBus Clock from 14.31818 MHz Divider
1 SMBus Clock from RTC 32.768 KHz ... defult
6 Reserved ........................................ always reads 0
5 Internal PLL Reset During Suspend
0 Enable.................................................... default
1 Disable
4 SUSST1# / GPO3 Select (Pin Y3)
0 SUSST1#............................................... default
1 GPO3
3 GPO2 / SUSB# Select (Pin AF2)
0 SUSB#................................................... default
1 GPO2
2 GPO1 / SUSA# Select (Pin AA2)
0 SUSA# .................................................. default
1 GPO1
1-0 GPO0 Output Select (Pin AA3)
This field controls the GPO0 output signal for Pulse
Width Modulation.
00 GPO0 Fixed Output Level (defined by PMIO
Rx4C[0]) ............................................... default
01 GPO0 output is 1 Hz “SLOWCLK”
10 GPO0 output is 4 Hz “SLOWCLK”
11 GPO0 output is 16 Hz “SLOWCLK”
Offset 95 – Miscellaneous Power Well Control.............. RW
7 CPUSTP# to SUSST# Delay Select
This bit controls the delay between the deassertion of
CPUSTP# and the deassertion of SUSST# during a
resume.
0 1 msec minimum ...................................default
1 125 usec minimum
6 SUSST# Deasserted Before PWRGD for STD
0 Disable...................................................default
1 Enable (SUST# is deasserted before PWRGD
when resuming from STD)
5 Keyboard / Mouse Port Swap
This bit determines whether the keyboard and mouse
ports can be swapped.
0 Disable...................................................default
1 Enable
4 Reserved ........................................always reads 0
3 SMB2 / GPO Select
0 SMBDT2 / SMBCK2 ............................default
1 GPO26 / GPO27
2 AOL 2 SMB Slave
This bit controls whether external SMB masters can
access internal SMB registers (for Alert-On-LAN).
0 Enable (external SMB masters may reset /
resume the system (when Rx96[4]=1) or detect
GPI status) .............................................default
1 Disable
1 SUSCLK / GPO4 Select
0 SUSCLK................................................default
1 GPO4
0 USB Wakeup for STR / STD / SoftOff
This bit controls whether USB Wakeup is enabled
when PMIO Rx21-20[14] (USB Wakeup Status) = 1.
This allows wakeup from STR, STD, Soft Off, and
POS.
0 Disable...................................................default
1 Enable
Offset 96 – Power On / Reset Control............................. RW
7-4 Reserved ........................................always reads 0
3-0 CPU Frequency Strapping Value Output to NMI,
INTR, IGNNE#, and A20M# during RESET#
The value written to this field is strapped through
NMI, INTR, IGNNE#, and A20M# during RESET#
to determine the multiplier for setting the CPU’s
internal frequency. If the CPU hangs due to
inappropriate settings written here, the GP3 timer
(second timeout) can be used to initiate a system
reboot (PMIO Rx42[2] = 1). Refer to the BIOS
Porting Guide for additional details.