Product specifications

VT8235 V-Link South Bridge
Revision 1.22 October 24, 2002 -75- Device 17 Function 0 Power Management Registers
Offset 8B-88 – Power Management I/O Base..................RW
31-16 Reserved ........................................ always reads 0
15-7 Power Management I/O Register Base Address
Port Address for the base of the 128-byte Power
Management I/O Register block, corresponding to
AD[15:7]. See “Power Management I/O Space
Registers” in this document for definitions of the
registers in the Power Management I/O Register
Block
6-0 0000001b
Offset 8C – Host Bus Power Management Control........RW
7-4 Thermal Duty Cycle
This field determines the duty cycle of STPCLK#
when the THRM# pin is asserted. The duty cycle
indicates the percentage of performance (the lower
the percentage, the lower the performance and the
higher the power savings). The STPCLK# duty cycle
when THRM# is NOT asserted is controlled by
PMIO Rx10[3:0]. If the setting in that field is lower
than the setting in this field, the lower setting will be
used for thermal duty cycle.
0000 Reserved................................................ default
0001 0-6.25%
0010 6.25-12.50%
0011 18.75-25.00%
0100 31.25-37.50%
0101 37.50-43.75%
0110 43.75-50.00%
0111 50.00-56.25%
1000 56.25-62.50%
1001 62.50-68.75%
1010 68.75-75.00%
1011 75.00-87.50%
1100 75.00-81.25%
1101 81.25-87.50%
1110 87.50-93.75%
1111 93.75-100%
3 THRM Enable
0 Disable .................................................. default
1 Enable
2 Processor Break Event
0 Disable .................................................. default
1 Enable
1-0 Reserved ........................................ always reads 0
Offset 8D – Throttle / Clock Stop Control...................... RW
7 Throttle Timer Reset......................................def = 0
6-5 Throttle Timer
This field determines the number of bits used for the
throttle timer, which in conjunction with the throttle
timer tick determines the cycle time of STPCLK#.
For example, if a 2-bit timer and a 7.5 usec timer tick
are selected, the STPCLK# cycle time would be 30
usec (2**2 x 7.5). If a 4-bit timer and a 7.5 usec
timer tick is selected, the cycle time would be 120
usec (2**4 x 7.5).
0x 4-Bit ....................................................default
10 3-Bit
11 2-Bit
4 Fast Clock (7.5us) as Throttle Timer Tick
This bit controls whether the throttle timer tick uses
7.5 usec as its time base (120 usec cycle time when
using a 4-bit timer).
0 Timer Tick is selected by Rx80[1] ........default
1 Timer Tick is 7.5 usec (Rx80[1] is ignored)
3 SMI Level Output (Low)
0 Disable...................................................default
1 Enable (during an SMI event, SMI# is held
low until SMI event status is cleared)
2 Internal Clock Stop for PCI Idle
This bit controls whether the internal PCI clock is
stopped when PCKRUN# is high.
0 PCI clock is not stopped ........................default
1 PCI clock is stopped
1 Internal Clock Stop During C3
This bit controls whether the internal PCI clock is
stopped during C3 state.
0 PCI clock is not stopped ........................default
1 PCI clock is stopped
0 Internal Clock Stop During Suspend
This bit controls whether the internal PCI clock is
stopped during Suspend state.
0 PCI clock is not stopped ........................default
1 PCI clock is stopped