Product specifications

VT8235 V-Link South Bridge
Revision 1.22 October 24, 2002 -72- Device 17 Function 0 Power Management Registers
Power Management-Specific Configuration Registers
Offset 80 – General Configuration 0 (00h)......................RW
7 Reserved ........................................ always reads 0
6 Sleep Button
0 Disable .................................................. default
1 Sleep Button is on GPI21 / ACSDIN3 pin (V1)
5 Debounce LID and PWRBTN# Inputs for 200us
This bit controls whether the debounce circuit for the
LID# and PWRBTN# inputs is enabled to reduce
possible noise.
0 Disable .................................................. default
1 Enable
4 Reserved (Do Not Program).................... default = 0
3 Microsoft Sound Monitor in Audio Access
This bit controls whether an I/O access to the sound
port sets I/O Rx33-30[10] (Audio Access Status) = 1.
0 Disable .................................................. default
1 Enable
2 Game Port Monitor in Audio Access
This bit controls whether an I/O access to the game
port sets I/O Rx33-30[10] (Audio Access Status) = 1.
0 Disable .................................................. default
1 Enable
1 Sound Blaster Monitor in Audio Access
This bit controls whether an I/O access to the sound
blaster port sets I/O Rx33-30[10] (Audio Access
Status) = 1.
0 Disable .................................................. default
1 Enable
0 MIDI Monitor in Audio Access
This bit controls whether an I/O access to the MIDI
port sets I/O Rx33-30[10] (Audio Access Status) = 1.
0 Disable .................................................. default
1 Enable
Offset 81 - General Configuration 1 (04h)...................... RW
7 I/O Enable for ACPI I/O Base
0 Disable access to ACPI I/O block.......... default
1 Allow access to Power Management I/O
Register Block (see offset 4B-48 to set the
base address for this register block). The
definitions of the registers in the Power
Management I/O Register Block are included
later in this document, following the Power
Management Subsystem overview.
6-4 Reserved ........................................always reads 0
3 ACPI Timer Count Select
0 24-bit Timer........................................... default
1 32-bit Timer
2 RTC Enable Signal Gated with PSON (SUSC#) in
Soft-Off Mode
This bit controls whether RTC control signals are
gated during system suspend state. This is to prevent
CMOS and Power-Well register data from being
corrupted during system on/off when the control
signals (PWRGD) may not be stable.
0 Disable
1 Enable...................................................default
1 Clock Throttling Clock Select (STPCLK#)
This bit controls the timer tick base for the throttle
timer.
0 30 usec (480 usec cycle time when using a 4-
bit timer) ................................................default
1 1 msec (16 msec cycle time when using a 4-bit
timer)
The timer tick base can be further lowered to 7.5 usec
(120 usec cycle time when using a 4-bit timer) by
setting Rx8D[4] = 1. When Rx8D[4] = 1, the setting
of this bit is ignored.
0 Reserved (Do Not Program) ....................default = 0