Product specifications

VT8235 V-Link South Bridge
Revision 1.22 October 24, 2002 -69- Device 17 Function 0 Bus Control Registers
Programmable Chip Select Control
Offset 5D-5C – PCS 0 I/O Port Address (0000h)............RW
15-0 PCS 0 I/O Port Address........................... default = 0
Offset 5F-5E – PCS 1 I/O Port Address (0000h).............RW
15-0 PCS 1 I/O Port Address........................... default = 0
Offset 61-60 – PCS 2 I/O Port Address (0000h)..............RW
15-0 PCS 2 I/O Port Address........................... default = 0
Offset 63-62 – PCS 3 I/O Port Address (0000h)..............RW
15-0 PCS 3 I/O Port Address........................... default = 0
Offset 65-64 – PCS I/O Port Address Mask (0000h)......RW
15-12 PCS 3 I/O Port Address Mask 3-0
0000 Decode range is 1 byte .......................... default
0001 Decode range is 2 bytes
0011 Decode range is 4 bytes
0111 Decode range is 8 bytes
1111 Decode range is 16 bytes
11-8 PCS 2 I/O Port Address Mask 3-0
0000 Decode range is 1 byte .......................... default
0001 Decode range is 2 bytes
0011 Decode range is 4 bytes
0111 Decode range is 8 bytes
1111 Decode range is 16 bytes
7-4 PCS 1 I/O Port Address Mask 3-0
0000 Decode range is 1 byte .......................... default
0001 Decode range is 2 bytes
0011 Decode range is 4 bytes
0111 Decode range is 8 bytes
1111 Decode range is 16 bytes
3-0 PCS 0 I/O Port Address Mask 3-0
0000 Decode range is 1 byte .......................... default
0001 Decode range is 2 bytes
0011 Decode range is 4 bytes
0111 Decode range is 8 bytes
1111 Decode range is 16 bytes
Offset 66 – PCS Control (00h) .........................................RW
7 PCS 3 Internal I/O
0 Disable (External)..................................default
1 Enable (Internal)
6 PCS 2 Internal I/O
0 Disable (External)..................................default
1 Enable (Internal)
5 PCS 1 Internal I/O
0 Disable (External)..................................default
1 Enable (Internal)
4 PCS 0 Internal I/O
0 Disable (External)..................................default
1 Enable (Internal)
The above 4 bits determine whether Programmable Chip
Selects 0-3 are treated as internal I/O
3 PCS 3
0 Disable...................................................default
1 Enable
2 PCS 2
0 Disable...................................................default
1 Enable
1 PCS 1
0 Disable...................................................default
1 Enable
0 PCS 0
0 Disable...................................................default
1 Enable
Offset 67 – Output Control (04h) ....................................RW
7-3 Reserved ........................................always reads 0
2 FERR Voltage
0 2.5V
1 1.5V ...................................................default
1-0 Reserved ........................................always reads 0