Product specifications

VT8235 V-Link South Bridge
Revision 1.22 October 24, 2002 -68- Device 17 Function 0 Bus Control Registers
Offset 5A – DMA Bandwidth Control (00h)...................RW
7 DMA Channel 7 Bandwidth
0 Normal .................................................. default
1 Improved
6 DMA Channel 6 Bandwidth
0 Normal .................................................. default
1 Improved
5 DMA Channel 5 Bandwidth
0 Normal .................................................. default
1 Improved
4 DMA Single Transfer Mode Bandwidth
0 Normal .................................................. default
1 Improved
3 DMA Channel 3 Bandwidth
0 Normal .................................................. default
1 Improved
2 DMA Channel 2 Bandwidth
0 Normal .................................................. default
1 Improved
1 DMA Channel 1 Bandwidth
0 Normal .................................................. default
1 Improved
0 DMA Channel 0 Bandwidth
0 Normal .................................................. default
1 Improved
The above bits determine if DMA bandwidth is improved for
the specified channel. If enabled, bandwidth improvement is
accomplished by reducing the transaction latency between the
DMA Controller and the LPC Bus Controller.
Offset 5B – Miscellaneous Control 2 (01h) ..................... RW
7-4 Reserved ........................................always reads 0
3 Bypass APIC De-Assert Message
0 Disable...................................................default
1 Enable
2 APIC HyperTransport Mode
0 Disable...................................................default
1 Enable
1 INTE#, INTF#, INTG#, INTH# (pins GPIO12-15)
0 Disable...................................................default
1 Enable
0 Dynamic Clock Stop
0 Disable
1 Enable...................................................default