Product specifications

VT8235 V-Link South Bridge
Revision 1.22 October 24, 2002 -67- Device 17 Function 0 Bus Control Registers
GPIO and Miscellaneous Control
Offset 58 – Miscellaneous Control 0 (40h).......................RW
7 Reserved ........................................ always reads 0
6 Internal APIC
0 Disable
1 Enable....................................................default
5 South Bridge Interrupt Cycles Run at 33 MHz
0 Disable .................................................. default
1 Enable
4 Address Decode
0 Subtractive............................................. default
1 Positive
3 RTC High Bank Access
0 Disable access to upper 128 bytes......... default
1 Enable access to upper 128 bytes
2 RTC Rx32 Write Protect
0 Disable (not protected).......................... default
1 Enable (write protected)
1 RTC Rx0D Write Protect
0 Disable (not protected).......................... default
1 Enable (write protected)
0 RTC Rx32 Map to Century Byte
Controls whether RTC Rx32 is mapped to the
century byte.
0 Disable .................................................. default
1 Enable
Offset 59 – Miscellaneous Control 1 (00h)...................... RW
7-6 Reserved ........................................always reads 0
5 LPC RTC
0 Disable...................................................default
1 Enable
4 LPC Keyboard
0 Disable (ISA Keyboard) ........................default
1 Enable (LPC Keyboard)
3 External MCCS to LPC
Controls whether external MCCS is through LPC or
ISA when internal MCCS is not used.
0 Disable (ISA MCCS).............................default
1 Enable (LPC MCCS)
2 Internal MCCS (Microcontroller Chip Select)
0 Disable (external MCCS) ......................default
1 Enable (internal MCCS)
1 A20M# Active
0 Disable (A20M# signal not asserted)..... default
1 Enable (A20M# signal asserted)
0 NMI on PCI Parity Error
0 Disable...................................................default
1 Enable (to generate NMI, Port 61[3] and Port
70[7] must also be set)