Product specifications

VT8235 V-Link South Bridge
Revision 1.22 October 24, 2002 -66- Device 17 Function 0 Bus Control Registers
Serial IRQ, LPC, and PC/PCI DMA Control
Offset 52 – Serial IRQ & LPC Control (00h)..................RW
7 Reserved ........................................ always reads 0
6 LPC Short Wait Abort
0 Disable .................................................. default
1 Enable. During a short wait, the cycle is
aborted after 8Ts.
5 LPC Frame Wait State Time
0 Frame Wait State is 1T.......................... default
1 Frame Wait State is 2T
4 LPC Stop to Start Frame Wait State
0 Enable. One idle state is inserted between
Stop and Start........................................ default
1 Disable. Stop is followed immediately by
Start.
3 Serial IRQ
0 Disable .................................................. default
1 Enable (IRQ asserted via SerialIRQ pin AE10)
2 Serial IRQ Quiet Mode
0 Continuous Mode.................................. default
1 Quiet Mode
1-0 Serial IRQ Start-Frame Width
00 4 PCI Clocks ......................................... default
01 6 PCI Clocks
10 8 PCI Clocks
11 10 PCI Clocks
Offset 53 – PC/PCI DMA Control ...................................RW
7 PCI DMA Pair A and Pair B
0 Disable .................................................. default
1 Enable
6 PCI DMA Channel 7
0 Disable .................................................. default
1 Enable
5 PCI DMA Channel 6
0 Disable .................................................. default
1 Enable
4 PCI DMA Channel 5
0 Disable .................................................. default
1 Enable
3 PCI DMA Channel 3
0 Disable .................................................. default
1 Enable
2 PCI DMA Channel 2
0 Disable .................................................. default
1 Enable
1 PCI DMA Channel 1
0 Disable .................................................. default
1 Enable
0 PCI DMA Channel 0
0 Disable .................................................. default
1 Enable
Plug and Play Control - PCI
Offset 54 - PCI Interrupt Polarity................................... RW
7-4 Reserved ........................................always reads 0
The following bits all default to “level” triggered (0)
3 PCI INTA# Invert (edge) / Non-invert (level). (1/0)
2 PCI INTB# Invert (edge) / Non-invert (level) . (1/0)
1 PCI INTC# Invert (edge) / Non-invert (level). (1/0)
0 PCI INTD# Invert (edge) / Non-invert (level). (1/0)
Note: PCI INTA-D# normally connect to PCI interrupt pins
INTA-D# (see pin definitions for more information).
Offset 55 – PCI PNP Interrupt Routing 1 ...................... RW
7-4 PCI INTA# Routing (see PnP IRQ routing table)
3-0 Reserved ........................................always reads 0
Offset 56 – PCI PNP Interrupt Routing 2 ...................... RW
7-4 PCI INTC# Routing (see PnP IRQ routing table)
3-0 PCI INTB# Routing (see PnP IRQ routing table)
Offset 57 – PCI PNP Interrupt Routing 3 ...................... RW
7-4 PCI INTD# Routing (see PnP IRQ routing table)
3-0 Reserved ........................................always reads 0
Table 11. PnP IRQ Routing Table
0000 Disabled.................................................default
0001 IRQ1
0010 Reserved
0011 IRQ3
0100 IRQ4
0101 IRQ5
0110 IRQ6
0111 IRQ7
1000 Reserved
1001 IRQ9
1010 IRQ10
1011 IRQ11
1100 IRQ12
1101 Reserved
1110 IRQ14
1111 IRQ15