Product specifications

VT8235 V-Link South Bridge
Revision 1.22 October 24, 2002 -63- Device 17 Function 0 Bus Control Registers
Offset 48 – Read Pass Write Control...............................RW
7 APIC FSB Fixed at Low DW
0 Disable (Address Bit-2 not masked)...... default
1 Enable (force A2 from APIC FSB to low)
Address bit A2 controls whether data is in the lower
(0) or upper (1) doubleword of a quadword sent to
the CPU. When this bit is enabled, A2 is masked
which means it is always 0 to select the lower
doubleword.
6-4 Reserved ........................................ always reads 0
3 AC97 / LPC Read Pass Write
0 Disable (a read cannot be performed before a
preceeding write has been completed) .. default
1 Enable (internal AC97 and LPC devices are
allowed to perform a read before a preceeding
write)
2 IDE Read Pass Write
0 Disable (a read cannot be performed before a
preceeding write has been completed) .. default
1 Enable (the internal IDE controller is allowed
to perform a read before a preceeding write)
1 USB Read Pass Write
0 Disable (a read cannot be performed before a
preceeding write has been completed) .. default
1 Enable (the internal USB controllers are
allowed to perform a read before a preceeding
write)
0 NIC Read Pass Write
0 Disable (a read cannot be performed before a
preceeding write has been completed) .. default
1 Enable (the internal LAN controller is allowed
to perform a read before a preceeding write)
Offset 49 – CCA Control.................................................. RW
7 Reserved ........................................always reads 0
6 South Bridge Internal Master Devices Priority
Higher Than External PCI Master
0 Disable...................................................default
1 Enable
The “CCA” is an internal arbiter that controls the
priority of external PCI masters vs. internal master
devices. Normally priority is the same for internal
and external PCI master devices, but when this bit is
enabled, internal master devices are given higher
priority than external PCI masters (3/4 : 1/4).
5 CCA Clean to Mask Off IRQ
Controls whether interrupt requests are gated until
data is written to memory.
0 Disable...................................................default
1 Enable
4-3 Reserved (Do Not Program) ....................default = 0
2 WSC Mask Off INTR
Controls whether INTR is masked until write snoop
is complete.
0 Disable...................................................default
1 Enable
1-0 Reserved (Do Not Program) ....................default = 0