Product specifications

VT8235 V-Link South Bridge
Revision 1.22 October 24, 2002 -62- Device 17 Function 0 Bus Control Registers
ISA Bus Control
Offset 40 - ISA Bus Control (00h)....................................RW
7 ISA Command Delay
0 Normal .................................................. default
1 Extra
6 I/O Recovery Time
The number of clocks between 2 I/O commands
0 Disable .................................................. default
1 Enable (Rx4C[7:6] determines the # of clocks)
5 ROM Wait States
0 1 Wait State........................................... default
1 0 Wait States
4 ROM Write
0 Disable (ROM writes are ignored) ........ default
1 Enable (ROM can be written)
3 Double DMA Clock
0 DMA clock runs at 4 MHz.................... default
1 DMA clock runs at 8 MHz
2 4D0 / 4D1 Port Configuration
Controls whether ports 4D0 / 4D1 can be configured.
Ports 4D0 / 4D1 determine whether IRQ requests are
edge or level triggerred (4D0[7-0] for IRQ7-0,
4D1[7-0] for IRQ15-8) (0 = level, 1 = edge).
0 Disable .................................................. default
1 Enable
1 DMA / Interrupt / Timer Shadow Register Read
0 Disable .................................................. default
1 Enable (shadow register values can be read)
0 Double ISA Bus Clock
0 Bus clock runs at PCLK / 4 (8 MHz) .... default
1 Bus clock runs at PCLK / 2 (16 MHz)
Offset 41 – BIOS ROM Decode Control (00h)................RW
Setting these bits to 1 enables the indicated address range to be
included in the ROMCS# decode:
7 000E0000h-000EFFFFh.............. default=0 (disable)
6 FFF00000h-FFF7FFFFh ............ default=0 (disable)
5 FFE80000h-FFEFFFFFh............ default=0 (disable)
4 FFE00000h-FFE7FFFFh............ default=0 (disable)
3 FFD80000h-FFDFFFFFh .......... default=0 (disable)
2 FFD00000h-FFD7FFFFh ........... default=0 (disable)
1 FFC80000h-FFCFFFFFh .......... default=0 (disable)
0 FFC00000h-FFC7FFFFh............ default=0 (disable)
Note: ROMCS# is always active when ISA addresses
FFF80000-FFFFFFFF and 000F0000-000FFFFF are decoded.
Offset 42 – Line Buffer Control (00h)............................. RW
7 ISA Master DMA Line Buffer
Controls whether the DMA line buffer is used.
0 Disable...................................................default
1 Enable. Master DMA waits until the line
buffer is full (8 DWords) before transmitting
data (bit-6 must also be enabled to insure that
there are no coherency issues).
6 Gate Interrupt Until Line Buffer Flush Complete
This bit should be enabled if bit-7 is enabled.
0 Disable...................................................default
1 Enable. IRQs are gated until the line buffer is
flushed to insure that there are no coherency
issues.
5 Flush Line Buffer for Interrupt
This bit controls whether the line bufer is flushed
when an interrupt request is generated. This bit
should be enabled if bit-7 is enabled.
0 Disable...................................................default
1 Enable
4 Uninterruptable Burst Read
0 Disable...................................................default
1 Enable. The PCI bus is not granted to DMA
until burst read transactions from the north
bridge are completed.
3 Gate IRQ Until Line Bufer Flush Completed
0 Disable...................................................default
1 Enable
2-0 Reserved ........................................always reads 0
Offset 43 – Delay Transaction Control (00h).................. RW
7-4 Reserved (Do Not Program) ....................default = 0
3 Delayed Transactions (PCI Spec Rev 2.1)
This bit controls whether delayed transactions
(delayed read / write and posted write) are enabled.
0 Disable...................................................default
1 Enable
2 Only Posted Write
This bit controls whether posted write is enabled, as
opposed to bit-3 which controls whether delayed read
/ write as well as posted write are enabled.
0 Disable...................................................default
1 Enable
1 Write Delay Transaction Timeout Timer
When enabled, if a delayed transaction (write cycle
only) is not retried after 2
12
PCI clocks, the
transaction is terminated.
0 Disable...................................................default
1 Enable
0 Read Delay Transaction Timeout Timer
When enabled, if a delayed transaction (read cycle
only) is not retried after 2
12
PCI clocks, the
transaction is terminated.
0 Disable...................................................default
1 Enable