Product specifications

VT8235 V-Link South Bridge
Revision 1.22 October 24, 2002 -56- Device 16 Function 2 USB UHCI Registers for Ports 4-5
Offset 42 - Miscellaneous Control 3 (03h).......................RW
7 Reserved (Do Not Program).................... default = 0
6-5 Reserved ........................................ always reads 0
4 SubVendor ID / SubDevice ID Backdoor
0 Rx2C-2F RO ......................................... default
1 Rx2C-2F RW
3-2 Reserved (Do Not Program).................... default = 0
1-0 Reserved .................................. always reads 11b
Offset 43 - Miscellaneous Control 4 (00h).......................RW
7-5 Reserved ........................................ always reads 0
4 Reserved (Do Not Program).................... default = 0
3 Continue Transmission of Erroneous Data on
FIFO Underrun
0 Enable.................................................... default
1 Disable
2 Issue CRC Error Instead of Stuffing Error on
FIFO Underrun
0 Enable.................................................... default
1 Disable
1-0 Reserved ........................................ always reads 0
Offset 48 - Miscellaneous Control 5.................................RW
7-5 Reserved ........................................ always reads 0
4-3 Reserved (Do Not Program).................... default = 0
2 Issue Bad CRC5 in SOF After FIFO Underrun
0 Enable.................................................... default
1 Disable
1 Lengthen PreSOF Time
The preSOF time point determines whether there is
enough timein the remaining frame period to perform
a 64-byte transaction. It prevents a packet that may
not fit in the remaining frame period from being
initiated. This bit controls whether the preSOF time
point is moved back so that the preSOF time is
lengthened.
0 Disable .................................................. default
1 Enable (PreSOF time lengthened)
0 Issue Nonzero Bad CRC Code on FIFO Underrun
A FIFO underrun occurs when there is no data in the
FIFO to supply data transmission. When this occurs,
the south bridge invalidates the data by sending an
incorrect CRC code to the device. This bit controls
the type of incorrect CRC sent.
0 Non zero CRC (recommended)............. default
1 All zero CRC
This option isn’t really needed any more as non-zero
CRC always works.
Offset 49 - Miscellaneous Control 6 (03h)....................... RW
7-6 Reserved ........................................always reads 0
5-4 Reserved (Do Not Program) ....................default = 0
3-2 Reserved ........................................always reads 0
1 EHCI Supports PME Assertion in D3 Cold State
0 Not Supported
1 Supported..............................................default
0 UHCI Supports PME Assertion in D3 Cold State
0 Not Supported
1 Supported..............................................default
Offset 4A - Miscellaneous Control 7 (00h)...................... RW
7-3 Reserved ........................................always reads 0
2 Reserved (Do Not Program) ....................default = 0
1 Reserved ........................................always reads 0
0 Use External 60 MHz Clock
0 Disable...................................................default
1 Enable
Offset 60 - Serial Bus Release Number ............................RO
7-0 Release Number..............................always reads 10h
Offset 84 – PM Capability Status.................................... RW
7-0 PM Capability Status
00 D0 .................................................... default
01 -reserved-
10 -reserved-
11 D3 Hot
Offset C1-C0 - Legacy Support ........................................RO
15-0 UHCI v1.1 Compliant ................always reads 2000h