Product specifications

VT8235 V-Link South Bridge
Revision 1.22 October 24, 2002 -44- Memory Mapped I/O APIC Registers
Offset 3F-10 – I/O Redirection Table
This table contains 24 registers, with one dedicated table entry
for each of the 24 APIC interrupt signals. Each 64-bit register
consists of two 32-bit values at consecutive index locations,
with the low 32 bits at the even index and the upper 32 bits at
the odd index. The default value for all registers is xxx1 xxxx
xxxx xxxxh.
Offset 11-10 – I/O Redirection – APIC IRQ0 .................RW
Offset 13-12 – I/O Redirection – APIC IRQ1 .................RW
Offset 15-14 – I/O Redirection – APIC IRQ2 .................RW
Offset 17-16 – I/O Redirection – APIC IRQ3 .................RW
Offset 19-18 – I/O Redirection – APIC IRQ4 .................RW
Offset 1B-1A – I/O Redirection – APIC IRQ5................RW
Offset 1D-1C – I/O Redirection – APIC IRQ6................RW
Offset 1F-1E – I/O Redirection – APIC IRQ7 ................RW
Offset 21-20 – I/O Redirection – APIC IRQ8 .................RW
Offset 23-22 – I/O Redirection – APIC IRQ9 .................RW
Offset 25-24 – I/O Redirection – APIC IRQ10 ...............RW
Offset 27-26 – I/O Redirection – APIC IRQ11 ...............RW
Offset 29-28 – I/O Redirection – APIC IRQ12 ...............RW
Offset 2B-2A – I/O Redirection – APIC IRQ13..............RW
Offset 2D-2C – I/O Redirection – APIC IRQ14..............RW
Offset 2F-2E – I/O Redirection – APIC IRQ15 ..............RW
Offset 31-30 – I/O Redirection – APIC IRQ16 ...............RW
Offset 33-32 – I/O Redirection – APIC IRQ17 ...............RW
Offset 35-34 – I/O Redirection – APIC IRQ18 ...............RW
Offset 37-36 – I/O Redirection – APIC IRQ19 ...............RW
Offset 39-38 – I/O Redirection – APIC IRQ20 ...............RW
Offset 3B-3A – I/O Redirection – APIC IRQ21..............RW
Offset 3D-3C – I/O Redirection – APIC IRQ22..............RW
Offset 3F-3E – I/O Redirection – APIC IRQ23 ..............RW
Format for Each I/O Redirection Table Entry:
Physical Mode (bit-11=0)
63-60 Reserved ........................................always reads 0
59-56 APIC ID ................................ default = undefined
Logical Mode (bit-11=1)
63-56 Destination ................................default = undefined
55-17 Reserved ........................................always reads 0
16 Interrupt Masked
0 Not masked............................................default
1 Masked
15 Trigger Mode
0 Edge Sensitive .......................................default
1 Level Sensitive
14 Remote IRR (Level Sensitive Interrupts Only).RO
0 EOI message with a matching interrupt vector
received from a local APIC
1 Level sensitive interrupt sent by IOAPIC
accepted by local APIC(s)
13 Interrupt Input Pin Polarity
0 Active High............................................default
1 Active Low
12 Delivery Status.....................................................RO
Contains the current status of the delivery of this
interrupt.
0 Idle (no activity)
1 Send Pending (the interrupt has been injected
but its delivery is temporarily delayed either
because the APIC bus is busy or because the
receiving APIC unit cannot currently accept
the interrupt)
11 Destination Mode
Determines the interpretation of bits 56-63.
0 Physical Mode .......................................default
1 Logical Mode
10-8 Delivery Mode
Specifies how the APICs listed in the destination
field should act upon reception of this signal
000 Fixed ....................................................default
001 Lowest Priority
010 SMI
011 -reserved-
100 NMI
101 INIT
110 -reserved-
111 External INT
7-0 Interrupt Vector
Contains the interrupt vector for this interrupt.
Vector values range from 10h to FEh.