Product specifications

VT8235 V-Link South Bridge
Revision 1.22 October 24, 2002 -39- Legacy I/O Registers
DMA Controller I/O Registers
Ports 00-0F - Master DMA Controller
Channels 0-3 of the Master DMA Controller control System
DMA Channels 0-3. There are 16 Master DMA Controller
registers:
I/O Address Bits 15-0
Register Name
0000 0000 000x 0000 Ch 0 Base / Current Address RW
0000 0000 000x 0001 Ch 0 Base / Current Count RW
0000 0000 000x 0010 Ch 1 Base / Current Address RW
0000 0000 000x 0011 Ch 1 Base / Current Count RW
0000 0000 000x 0100 Ch 2 Base / Current Address RW
0000 0000 000x 0101 Ch 2 Base / Current Count RW
0000 0000 000x 0110 Ch 3 Base / Current Address RW
0000 0000 000x 0111 Ch 3 Base / Current Count RW
0000 0000 000x 1000 Status / Command RW
0000 0000 000x 1001 Write Request WO
0000 0000 000x 1010 Write Single Mask WO
0000 0000 000x 1011 Write Mode WO
0000 0000 000x 1100 Clear Byte Pointer F/F WO
0000 0000 000x 1101 Master Clear WO
0000 0000 000x 1110 Clear Mask WO
0000 0000 000x 1111 R/W All Mask Bits RW
Ports C0-DF - Slave DMA Controller
Channels 0-3 of the Slave DMA Controller control System
DMA Channels 4-7. There are 16 Slave DMA Controller
registers:
I/O Address Bits 15-0
Register Name
0000 0000 1100 000x Ch 4 Base / Current Address RW
0000 0000 1100 001x Ch 4 Base / Current Count RW
0000 0000 1100 010x Ch 5 Base / Current Address RW
0000 0000 1100 011x Ch 5 Base / Current Count RW
0000 0000 1100 100x Ch 6 Base / Current Address RW
0000 0000 1100 101x Ch 6 Base / Current Count RW
0000 0000 1100 110x Ch 7 Base / Current Address RW
0000 0000 1100 111x Ch 7 Base / Current Count RW
0000 0000 1101 000x Status / Command RW
0000 0000 1101 001x Write Request WO
0000 0000 1101 010x Write Single Mask WO
0000 0000 1101 011x Write Mode WO
0000 0000 1101 100x Clear Byte Pointer F/F WO
0000 0000 1101 101x Master Clear WO
0000 0000 1101 110x Clear Mask WO
0000 0000 1101 111x Read/Write All Mask Bits WO
Note that not all bits of the address are decoded.
The Master and Slave DMA Controllers are compatible with
the Intel 8237 DMA Controller chip. Detailed description of
8237 DMA controller operation can be obtained from the Intel
Peripheral Components Data Book and numerous other
industry publications.
Ports 80-8F - DMA Page Registers
There are eight DMA Page Registers, one for each DMA
channel. These registers provide bits 16-23 of the 24-bit
address for each DMA channel (bits 0-15 are stored in
registers in the Master and Slave DMA Controllers). They are
located at the following I/O Port addresses:
I/O Address Bits 15-0
Register Name
0000 0000 1000 0111 Channel 0 DMA Page (M-0).........RW
0000 0000 1000 0011 Channel 1 DMA Page (M-1).........RW
0000 0000 1000 0001 Channel 2 DMA Page (M-2).........RW
0000 0000 1000 0010 Channel 3 DMA Page (M-3).........RW
0000 0000 1000 1111 Channel 4 DMA Page (S-0)...........RW
0000 0000 1000 1011 Channel 5 DMA Page (S-1)...........RW
0000 0000 1000 1001 Channel 6 DMA Page (S-2)...........RW
0000 0000 1000 1010 Channel 7 DMA Page (S-3) ..........RW
DMA Controller Shadow Registers
The DMA Controller shadow registers are enabled by setting
function 0 Rx77 bit 0. If the shadow registers are enabled,
they are read back at the indicated I/O port instead of the
standard DMA controller registers (writes are unchanged).
Port 0 –Channel 0 Base Address ......................................RO
Port 1 –Channel 0 Byte Count..........................................RO
Port 2 –Channel 1 Base Address ......................................RO
Port 3 –Channel 1 Byte Count..........................................RO
Port 4 –Channel 2 Base Address ......................................RO
Port 5 –Channel 2 Byte Count..........................................RO
Port 6 –Channel 3 Base Address ......................................RO
Port 7 –Channel 3 Byte Count..........................................RO
Port 8 –1
st
Read Channel 0-3 Command Register ..........RO
Port 8 –2
nd
Read Channel 0-3 Request Register..............RO
Port 8 –3
rd
Read Channel 0 Mode Register.....................RO
Port 8 –4
th
Read Channel 1 Mode Register .....................RO
Port 8 –5
th
Read Channel 2 Mode Register .....................RO
Port 8 –6
th
Read Channel 3 Mode Register .....................RO
Port F –Channel 0-3 Read All Mask................................RO
Port C4 –Channel 5 Base Address....................................RO
Port C6 –Channel 5 Byte Count.......................................RO
Port C8 –Channel 6 Base Address....................................RO
Port CA –Channel 6 Byte Count ......................................RO
Port CC –Channel 7 Base Address...................................RO
Port CE –Channel 7 Byte Count ......................................RO
Port D0 –1
st
Read Channel 4-7 Command Register........RO
Port D0 –2
nd
Read Channel 4-7 Request Register...........RO
Port D0 –3
rd
Read Channel 4 Mode Register ..................RO
Port D0 –4
th
Read Channel 5 Mode Register...................RO
Port D0 –5
th
Read Channel 6 Mode Register...................RO
Port D0 –6
th
Read Channel 7 Mode Register...................RO
Port DE –Channel 4-7 Read All Mask.............................RO