Product specifications

VT8235 V-Link South Bridge
Revision 1.22 October 24, 2002 -12- Pin Descriptions
LAN Controller - Media Independent Interface (MII)
Signal Name Pin # I/O PU Signal Description
MCOL
C13 I
PD
MII Collision Detect. From the external PHY.
MCRS
B13 I
PD
MII Carrier Sense. Asserted by the external PHY when the media is
active.
MDCK
C9 O
PD
MII Management Data Clock. Sent to the external PHY as a timing
reference for MDIO
MDIO
B9 IO
PD
MII Management Data I/O. Read from the MDI bit or written to the
MDO bit.
MRXCLK
B10 I
PD
MII Receive Clock. 2.5 or 25 MHz clock recovered by the PHY.
MRXD[3-0]
A9, D9, D10, E10 I
PD
MII Receive Data. Parallel receive data lines driven by the external
PHY synchronous with MRXCLK.
MRXDV
C10 I
PD MII Receive Data Valid.
MRXERR
A10 I
PD
MII Receive Error. Asserted by the PHY when it detects a data
decoding error.
MTXCLK
A12 I
PD
MII Transmit Clock. Always active 2.5 or 25 MHz clock supplied by
the PHY.
MTXD[3-0]
C11, B11, A11, C12 O
PD
MII Transmit Data. Parallel transmit data lines synchronized to
MTXCLK.
MTXENA
B12 O
PD
MII Transmit Enable. Signals that transmit is active from the MII
port to the PHY.
MIIVCC
D11, D12, E11, E12
Power
MII Interface Power. 3.3V ±5%.
MIIVCC25
D13, E13
Power
MII Suspend Power. 2.5V ±5%.
RAMVCC
E7
Power
Power For Internal LAN RAM. 2.5V ±5%.
RAMGND
E8
Power Ground For Internal LAN RAM.
Serial EEPROM Interface
Signal Name Pin # I/O PU Signal Description
EECS#
A13 O
Serial EEPROM Chip Select.
EECK
C14 O
Serial EEPROM Clock.
EEDO
A14 O
Serial EEPROM Data Output.
EEDI
B14 I
Serial EEPROM Data Input.
These pins are disabled if the SDCS1# pin is strapped low to enable serial EEPROM connection via the MII interface.
Low Pin Count (LPC) Interface
Signal Name Pin # I/O PU Signal Description
LFRM#
AE7 IO
LPC Frame.
LREQ#
AD7 IO
LPC DMA / Bus Master Request.
LAD[3-0]
AF7, AD8, AE8, AF8 IO PU
LPC Address / Data.
Note: Connect the LPC interface LPCRST# (LPC Reset) signal to PCIRST#
PC / PCI DMA
Signal Name Pin # I/O PU Signal Description
PCREQA / GPIO8 / VGATE C8 I
PC / PCI Request A. Device 17 Function 0 Rx53[7] = 1
PCREQB / GPIO9 B7 I
PC / PCI Request B. Device 17 Function 0 Rx53[7] = 1
PCGNTA / GPIO12 A7 O
PC / PCI Grant A. Device 17 Function 0 Rx53[7] = 1
PCGNTB / GPIO13 B8 O
PC / PCI Grant B. Device 17 Function 0 Rx53[7] = 1