Product specifications

VT8235 V-Link South Bridge
Revision 1.22 October 24, 2002 -133- Functional Descriptions
System Suspend States and Power Plane Control
There are three power planes inside the VT8235. The first
power plane (VSUS33) is always on unless turned off by the
mechanical switch. The second power plane (VCC) is
controlled by chip output SUSC# (also called “PSON”). The
third plane (VCCRTC) is powered by the combination of the
VSUS33 and the external battery (VBAT) for the integrated
real time clock. Most of the circuitry inside the VT8235 is
powered by VCC. The amount of logic powered by VSUS33
is very small; its main function is to control the supply of
VCC and other power planes. VCCRTC is always on unless
both the mechanical switch and VBAT are removed.
The VT8235 supports multiple system suspend states by
configuring the SLP_TYP field of ACPI I/O space register
Rx4-5:
a) POS (Power On Suspend): Most devices in the
system remain powered. The host bus is put into an
equivalent of the C3 state. In particular, the CPU is
put into the Stop Grant State or Stop Clock State
depending on the setting of the Host Stop bit.
SUSST1# is asserted to tell the north bridge to switch
to “Suspend DRAM Refresh” mode based on the
32KHz SUSCLK provided by the VT8235. As to the
PCI bus, setting the PCLK Run bit to 0 enables the
CLKRUN protocol defined in the PCI Mobile Design
Guide. That is, the PCKRUN# pin will be de-
activated after the PCI bus is idle for 26 clocks. Any
PCI bus masters including the north bridge may
resume PCI clock operation by pulling the
PCKRUN# pin low. During the PCKRUN# de-
activation period, the PCISTP# pin may be activated
to disable the output of the PCI clock generator if the
PCI_STP bit is enabled. When the system resumes
from POS, the VT8235 can optionally resume
without resetting the system, can reset the processor
only, or can reset the entire system. When no reset is
performed, the chip only needs to wait for the clock
synthesizer and processor PLL to lock before the
system is resumed, which typically takes 20ms.
b) STR (Suspend to RAM): Power is removed from
most of the system except the system DRAM. Power
is supplied to the suspend refresh logic in the north
bridge (e.g., VSUS25 of the VT8633) and the
suspend logic of the VT8235 (VSUS33).
c) STD (Suspend to Disk, also called Soft-off): Power
is removed from most of the system except the
suspend logic of VT8235 (VSUS33).
d) Mechanical Off: This is not a suspend state. All
power in the system is removed except the RTC
battery.
The suspend state is entered by setting the Sleep Enable bit to
1. Three power plane control signals (SUSA#, SUSB# and
SUSC#) are provided to turn off more system power planes as
the system moves to deeper power-down states, i.e., from
normal operation to POS (only SUSA# asserted), to STR (both
SUSA# and SUSB# asserted), and to STD (all three SUS#
signals asserted). In particular, the assertion of SUSC# can be
used to turn off the VCC supply to the VT8235.
One additional suspend status indicator (SUSST1#) is
provided to inform the north bridge and the rest of the system
of the processor and system suspend states. SUSST1# is
asserted when the system enters the suspend state or the
processor enters the C3 state. SUSST1# is connected to the
north bridge to switch between normal and suspend-DRAM-
refresh modes.
General Purpose I/O Ports
As ACPI compliant hardware, the VT8235 includes
PWRBTN#, SLPBTN#, and RI# pins to implement power
button, sleep button, and ring indicator functionality,
respectively. Furthermore, the VT8235 offers many general-
purpose I/O ports with the following capabilities:
• I
2
C / SMB Support
• Thermal Detect
• Notebook Lid Open / Close Detect
• Battery Low Detect
• Twelve General Purpose Input Ports (multiplexed with
other functions).
• Nineteen General Purpose Output Ports (1 dedicated
and 18 multiplexed with other functions)
• Four General Purpose Input / Output Ports
(multiplexed with other functions)
In addition, the VT8235 provides an external dedicated SMI
pin (EXTSMI#). The external SMI input can be programmed
to trigger an SCI or SMI at both the rising and falling edges of
the corresponding input signal. Software can check the status
of the input pin and take appropriate actions.