Product specifications

VT8235 V-Link South Bridge
Revision 1.22 October 24, 2002 -132- Functional Descriptions
FUNCTIONAL DESCRIPTIONS
Power Management
Power Management Subsystem Overview
The power management function of the VT8235 is indicated
in the following block diagram:
THRM#
Power
Plane and
System
Control
GP0
(Global
Standby)
Timer
PWRBTN#
RI#
SMI Arbiter
Sleep/Wake
State
Machine
SMI#
SCI#
- Legacy Only Event Logic
- ACPI / Legacy Event Logic
- ACPI Only Event Logic
- SMI Events
- SCI/SMI Events
Dec
0
1
CPU
STPCLK#
and ClkGen
Control
GP1
(Device
Idle)
Timer
User
Interface
Hardware
Events
RTC
SCI_EN
- ACPI / Legacy Generic Control Features
- ACPI / Legacy Fixed Control Features
- Wake-up Events
PM Timer
SCI Arbiter
Bus
Master
SLPBTN#
Primary
Events
USB resume
LID
GPIO
Hardware
Monitoring
Figure 3. Power Management Subsystem Block Diagram
Refer to ACPI Specification v1.0 and APM specification v1.2
for additional information.
Processor Bus States
The VT8235 supports the complete set of C0 to C3 processor
states as specified in the Advanced Configuration and Power
Interface (ACPI) specification (and defined in ACPI I/O space
Registers 10-15):
C0: Normal Operation
C1: CPU Halt (controlled by software).
C2: Stop Clock. Entered when the Processor Level 2
register (PMIO Rx14) is read. The STPCLK# signal
is asserted to put the processor in the Stop Grant
State. The CPUSTP# signal is not asserted so that
host clocks remain running. To exit this state, the
chip negates STPCLK#.
C3: Suspend. Entered when the Processor Level 3
register (PMIO Rx15) is read. In addition to
STPCLK# assertion as in the C2 state, the SUSST1#
(suspend status 1) signal is asserted to tell the north
bridge to switch to “Suspend DRAM Refresh” mode
based on the 32KHz suspend clock (SUSCLK)
provided by the VT8235. If the Host Stop bit is
enabled, then CPUSTP# is also asserted to stop clock
generation and put the CPU into Stop Clock State.
To exit this state, the chip negates CPUSTP# and
allows time for the processor PLL to lock. Then the
SUSST1# and STPCLK# signals are negated to
resume to normal operation.
During normal operation, two mechanisms are provided to
modulate CPU execution and control power consumption by
throttling the duty cycle of STPCLK#:
a. Setting the Throttle Enable bit to 1, the duty
cycle defined in Throttle Duty Cycle (PMIO
Rx10) is used.
b. THRM# pin assertion enables automatic clock
throttling with duty cycle pre-configured in
THRM# Duty Cycle (PCI configuration Rx4C).