Product specifications

VT8235 V-Link South Bridge
Revision 1.22 October 24, 2002 -131- Device 18 Function 0 LAN Registers
Offset A0 – Wake On LAN Control Set (00h)................RW
Offset A4 – Wake On LAN Control Clear (00h) ............RW
7 Link Off Detected (determines whether the system
wakes up from link off
detection)
6 Link On Detected (determines whether the system
wakes up from link on
detection)
5 Magic Packet Filter (determines whether the system
wakes up when a Magic Packet is detected)
4 Unicast Filter (determines whether the system wakes
up when a Unicast Packet is detected)
3 CRC3 Pattern Match Filtering (determines whether
the system wakes up when packet matching CRC3
pattern is detected)
2 CRC2 Pattern Match Filtering (determines whether
the system wakes up when packet matching CRC2
pattern is detected)
1 CRC1 Pattern Match Filtering (determines whether
the system wakes up when packet matching CRC1
pattern is detected)
0 CRC0 Pattern Match Filtering (determines whether
the system wakes up when packet matching CRC0
pattern is detected)
All bits above:
0 Disable .................................................. default
1 Enable
Offset A1 – Power Configuration Set (00h).....................RW
Offset A5 – Power Configuration Clear (00h) ................RW
7-6 Reserved ........................................ always reads 0
5 WOL Type
0 Driven by Level..................................... default
1 Driven By Pulse
4 Legacy WOL
0 Disable .................................................. default
1 Enable
3-2 Reserved ........................................ always reads 0
1-0 Reserved (Do Not Program).................... default = 0
Offset A3 – Wake On LAN Configuration Set (00h)..... RW
Offset A7 – Wake On LAN Configuration Clear (00h). RW
7 Force Power Management Enable over PME
Enable Bit (Legacy Use Only)
6 Full Duplex During Suspend
5 Accept Multicast During Suspend
This bit controls whether multicast packets are
accepted during suspend state. Whether a multicast
packet will actually wake up the system depends on
whether the packet is a type of packet set to wake up
the system, as determined by RxA0[5:0].
4 Accept Broadcast During Suspend
This bit controls whether broadcast packets are
accepted during suspend state. Whether a broadcast
packet will actually wake up the system depends on
whether the packet is a type of packet set to wake up
the system, as determined by RxA0[5:0].
3 MDC Acceleration
2 Extend Clock During Suspend
When enabled, the clock to the PHY is sent prior to
the start of data to allow more time for the PHY to
return to ready state.
1-0 Reserved ........................................always reads 0
All bits above:
0 Disable...................................................default
1 Enable
Offset B3-B0 – Pattern CRC0.......................................... RW
127-0 CRC0 Pattern ...........................................default = 0
Offset B7-B4 – Pattern CRC1.......................................... RW
127-0 CRC1 Pattern ...........................................default = 0
Offset BB-B8 – Pattern CRC2......................................... RW
127-0 CRC2 Pattern ...........................................default = 0
Offset BF-BC – Pattern CRC3 ........................................ RW
127-0 CRC3 Pattern ...........................................default = 0
Offset CF-C0 – Byte Mask 0............................................ RW
Offset DF-D0 – Byte Mask 1............................................ RW
Offset EF-E0 – Byte Mask 2.............................................RW
Offset FF-F0 – Byte Mask 3............................................. RW