Product specifications

VT8235 V-Link South Bridge
Revision 1.22 October 24, 2002 -127- Device 18 Function 0 LAN Registers
Offset 79 – Configuration 1 (00h).....................................RW
7 Transmit Frame Queueing
0 Enable (frames from the PCI bus can be
queued in the transmit FIFO – a maximum of
2 packets may be queued) ..................... default
1 Disable
6 Data Parity Generation and Checking
This bit controls whether PCI parity is enabled.
0 Enable.................................................... default
1 Disable
5 Memory-Read-Line Supported
This bit controls whether PCI Memory-Read-Line is
supported.
0 Enable.................................................... default
1 Disable
4 Transmit FIFO DMA Interleaved to Receiving
FIFO DMA After 32 DW Transaction
This bit controls whether during a transmit, priority
can be given to a receive transaction.
0 Disable .................................................. default
1 Enable (during a transmit, if a receive request
is seen, the transmit is paused after 32 DW’s
and priority is given to the receive)
3 Receive FIFO DMA Interleaved to Transmitting
FIFO DMA After 32 DW Transaction
This bit controls whether during a receive, priority
can be given to a transmit transaction.
0 Disable .................................................. default
1 Enable (during a receive, if a transmit request
is seen, the receive is paused after 32 DW’s
and priority is given to the transmit)
2 Memory Read Wait States (for ISA only)
0 None .................................................... default
1 Insert one wait state 2222
1 Memory Write Wait States s (for ISA only)
0 None .................................................... default
1 Insert one wait state 2222
0 Latency Timer
This bit controls whether PCI Delayed Transactions
are enabled.
0 Disable .................................................. default
1 Enable
Offset 7A – Configuration 2 (00h)................................... RW
7 Reserved ........................................always reads 0
6 Unused BootROM Address MA
This bit controls whether unused BootROM memory
address bits are tied high.
0 Not tied high .......................................... default
1 Tied high
5 Delayed Transactions for BootROM Memory
Read
This bit controls whether PCI delayed transactions
are enabled.
0 Disable...................................................default
1 Enable
4-0 Reserved ........................................always reads 0
Offset 7B – Configuration 3 (00h) ................................... RW
7 Memory Mapped I/O Access
0 Disable...................................................default
1 Enable
6-4 Reserved (Do Not Program) ....................default = 0
3 Backoff Algorithm
0 Fixed ....................................................default
1 Random
2 DEC Capture Effect Solution
0 Disable...................................................default
1 Enable
1 AMD Capture Effect Solution
0 Disable...................................................default
1 Enable
0 Backoff Algorithm Optional
0 Disable...................................................default
1 Enable