Product specifications

VT8235 V-Link South Bridge
Revision 1.22 October 24, 2002 -125- Device 18 Function 0 LAN Registers
Offset 6C – PHY Address (01h) .......................................RW
7-6 MII Management Polling Timer Interval (Polling
PHY)
00 1024 MDC Clock Cycles ...................... default
01 512 MDC Clock Cycles
10 128 MDC Clock Cycles
11 64 MDC Clock Cycles
MDC is an internal clock with a 960 ns cycle time.
5 Accelerate MDC Speed
0 Normal .................................................. default
1 4x Accelerated
4-0 Extended PHY Device Address..........default = 01h
Stored from EEPROM during power-up or EEPROM
auto-reload but can be programmed by software
Offset 6D – MII Status (13h)............................................RW
7 PHY Reset
0 PHY reset not asserted .......................... default
1 PHY reset asserted
6-5 Reserved ........................................ always reads 0
4 PHY Option
0 PHY address updated from EEPROM
1 Use default PHY address of 0001h .......default
3 PHY Device Received Error
0 No MII error.......................................... default
1 MII Error
2 Reserved ........................................ always reads 0
1 Link Failure
0 Link successful
1 Link unsuccessful (no connection)........default
0 PHY Speed
0 100 Mb
1 10 Mb ....................................................default
Offset 6E – Buffer Control 0 (00h).................................. RW
7-6 Reserved ........................................always reads 0
5-3 Rx FIFO Threshold Control
000 Determined by Offset 6 Rcv Ctrl Reg....default
~000 Determined by bits 2-0 of this register
2-0 DMA Length
000 32 bytes 8 DW................................default
001 64 bytes 16 DW
010 128 bytes 32 DW
011 256 bytes 64 DW
100 512 bytes 128 DW
101 1024 bytes 256 DW
11x Store & Forward
Offset 6F – Buffer Control 1 (00h) .................................. RW
7-6 Reserved ........................................always reads 0
5-3 Tx FIFO Threshold Control
000 Determined by Rx7 Transmit Control ...default
~000 Determined by this register
2-0 Polling Interval Timer
This field determines the polling interval when TD /
RD Auto-Polling is enabled (Rx09[3]=0).
000 4 PCI Clocks..........................................default
001 1 PCI Clock
010 2 PCI Clocks
011 8 PCI Clocks
100 16 PCI Clocks
101 32 PCI Clocks
110 64 PCI Clocks
111 128 PCI Clocks