Product specifications

VT8235 V-Link South Bridge
Revision 1.22 October 24, 2002 -122- Device 18 Function 0 LAN Registers
Offset 0C – Interrupt Status 0 (00h)................................RW
7 CRC or Miss Packet Tally Counter Overflow
Set if either counter overflows (both counters are 16
bits)
6 PCI Bus Error
Set if PCI bus error occurred.
5 Receive Buffer Link Error
Set when there is not enough buffer space for a
packet requiring multiple buffers.
4 Transmit Buffer Underflow
3 Transmit Error (Packet Transmit Aborted)
Set due to excessive collisions (more than 16),
transmit underflow, or transmit data linking error
2 Receive Error
Set due to CRC error, frame alignment error, FIFO
overflow, or received data linking error
1 Packet Transmitted Successfully
0 Packet Received Successfully
Offset 0D – Interrupt Status 1 (00h)................................RW
7 General Purpose Interrupt
This bit is set when there is a general purpose
interrupt event (Rx84). This bit is set when any bit in
Rx84 equals one and when its corresponding mask
bit in Rx86 also equals one.
6 Port State Change (PHY)
5 Transmit Abort Due to Excessive Collisions
Set when there is a transmit error that is due to
excessive collisions. Alternatively, Rx0C[3] is set
for all transmit errors.
4 Receive Buffer Full
Set when there is no more buffer space available in
system memory.
3 Receive Packet Race
Set when there is not enough room in the FIFO to
receive an additional packet.
2 Receive FIFO Overflow
1 Transmit FIFO Underflow
0 Early Receive Interrupt
Set if a packet is being received and Rx9[0] = 1.
Offset 0E – Interrupt Mask 0 (00h)................................. RW
Bits correspond to the bits in Interrupt Status Register 0. An
interrupt is generated when corresponding bits in both
registers equal 1.
Offset 0F – Interrupt Mask 1 (00h)................................. RW
Bits correspond to the bits in Interrupt Status Register 1. An
interrupt is generated when corresponding bits in both
registers equal 1.
Offset 17-10 – Multicast Address.....................................RW
The value in this register determines which Multicast
addresses are received.
Offset 1B-18 – RX Address .............................................. RW
This register reports the receive transcriptor address that is
being accessed.
Offset 1F-1C – TX Address.............................................. RW
This register reports the transmit transcriptor address that is
being accessed.