Product specifications

VT8235 V-Link South Bridge
Revision 1.22 October 24, 2002 -118- Device 18 Function 0 LAN Registers
Device 18 Function 0 Registers - LAN
All registers are located in the Device 18 Function 0 PCI
configuration space of the VT8235. These registers are
accessed through PCI configuration mechanism #1 via I/O
address CF8 / CFC.
PCI Configuration Space Header
Offset 1-0 - Vendor ID = 1106h........................................ RO
Offset 3-2 - Device ID = 3065h.......................................... RO
Offset 5-4 - Command.......................................................RW
15-3 Reserved ........................................ always reads 0
2 Bus Master ........................................ always reads 0
1 Memory Space.................................... always reads 0
0 I/O Space ......................................RW, default = 0
Offset 7-6 – Status (0400h)................................................ RO
15 Detected Parity Error........................ always reads 0
14 Signalled System Error...................... always reads 0
13 Received Master Abort...................... always reads 0
12 Received Target Abort....................... always reads 0
11 Signalled Target Abort...................... always reads 0
10-9 DEVSEL# Timing......................... fixed at 10 (slow)
8 Data Parity Detected.......................... always reads 0
7 Fast Back-to-Back Capable............... always reads 0
6 UDF Support ...................................... always reads 1
5 66 MHz Capable................................. always reads 1
4 Capabilities (e.g. PCI Pwr Mgmt) .... always reads 1
3-0 Reserved ........................................ always reads 0
Offset 8 - Revision ID (40h) .............................................. RO
Offset 9 - Program Interface ............................................ RO
Offset A - Sub Class Code................................................. RO
Offset B - Class Code ........................................................ RO
Offset C – Cache Line Size ...............................................RW
This register must be implemented by master devices that can
generate the memory-write-and-invalidate command.
Offset D – Latency Timer .................................................RW
This register must be implemented as writable by any master
that can burst more than two data phases.
Offset E - Header Type (00h) ........................................... RO
Offset F - BIST (00h)......................................................... RO
Offset 13-10 – I/O Base Address (0000 0000h)................RW
Offset 17-14 – Memory Base Address (0000 0000h).......RW
Offset 2B-28 – Card Bus CIS Pointer (0000 0000h) .......RW
Offset 33-30 – Expansion ROM Base (0000 0000h)........RW
Offset 34 – Capabilities Offset (40h) ................................RO
7-0 Capabilities Offset
Offset into the LAN function PCI space pointing to
the location of the first
item in the function’s
capability list.
Offset 3C - Interrupt Line................................................ RW
7-4 Reserved ........................................always reads 0
3-0 LAN Interrupt Routing
0000 Disabled.................................................default
0001 IRQ1
0010 Reserved
0011 IRQ3
0100 IRQ4
0101 IRQ5
0110 IRQ6
0111 IRQ7
1000 IRQ8
1001 IRQ9
1010 IRQ10
1011 IRQ11
1100 IRQ12
1101 IRQ13
1110 IRQ14
1111 Disabled
APIC
(See Device 17 Function 0 Rx4D[7])
x000 IRQ16
x001 IRQ17
x010 IRQ18
… …
x111 IRQ23
Offset 3D - Interrupt Pin (01h).........................................RO
7-0 Interrupt Routing Mode
00h Legacy mode interrupt routing
01h Native mode interrupt routing ............... default
LAN-Specific PCI Configuration Registers
Offset 40 – Capability ID (01h).........................................RO
7-0 Capability ID ..................................always reads 01h
Identifies the linked list item as being PCI power
management registers
Offset 41 – Next Item Pointer (00h)..................................RO
7-0 Next Item Pointer ...........................always reads 00h
Offset into the LAN function PCI space pointing to
the location of the next
item in the function’s
capability list.