Product specifications

VT8235 V-Link South Bridge
Revision 1.22 October 24, 2002 -111- Device 17 Function 5 Audio Controller Registers
Codec Command / Status SGD Registers
These registers are used to send commands to the codecs
I/O Offset 83-80 – AC97 Controller Cmd (W) / Status (R)
This register may be accessed from either function 5 or 6
31-30 Codec ID .........................................................RW
00 Select Codec CID = 00
01 Select Codec CID = 01
10 Select Codec CID = 10
11 Select Codec CID = 11
29 Codec 11 Data / Status / Index Valid..................RO
0 Not Valid
1 Valid (OK to Read bits 0-23)
28 Codec 10 Data / Status / Index Valid..................RO
0 Not Valid
1 Valid (OK to Read bits 0-23)
27 Codec 01 Data / Status / Index Valid..................RO
0 Not Valid
1 Valid (OK to Read bits 0-23)
26 Reserved ........................................ always reads 0
25 Codec 00 Data / Status / Index Valid..................RO
0 Not Valid
1 Valid (OK to Read bits 0-23)
24 AC97 Controller Busy .........................................RO
0 Codec is ready for a register access command
1 AC97 Controller is sending a command to the
codec (commands are not accepted)
23 Codec Register Read / Write Mode...................RW
0 Select Codec register write mode
1 Select Codec register read mode
22-16 Codec Register Index [7:1].................................RW
Index of the AC97 codec register to access (in the
attached codec). Data must be written before or at
the same time as Index because writing to the index
triggers the AC97 controller to access the addressed
codec register over the AC-link interface.
15-0 Codec Register Data............................................RW
I/O Offset 87-84 – Audio SGD Status Shadow ................RO
31 Audio Record 1 SGD Active Shadow.......(Rx70[7])
30 Audio Record 1 SGD Stop Shadow..........(Rx70[2])
29 Audio Record 1 SGD EOL Shadow.........(Rx70[1])
28 Audio Record 1 SGD Flag Shadow..........(Rx70[0])
27 Audio Record 0 SGD Active Shadow.......(Rx60[7])
26 Audio Record 0 SGD Stop Shadow..........(Rx60[2])
25 Audio Record 0 SGD EOL Shadow.........(Rx60[1])
24 Audio Record 0 SGD Flag Shadow..........(Rx60[0])
23-20 Reserved ........................................always reads 0
19 MultiChannel SGD Active Shadow..........(Rx40[7])
18 MultiChannel SGD Stop Shadow.............(Rx40[2])
17 MultiChannel SGD EOL Shadow............(Rx40[1])
16 MultiChannel SGD Flag Shadow.............(Rx40[0])
15 DX Channel 3 SGD Active Shadow .........(Rx30[7])
14 DX Channel 3 SGD Stop Shadow ............(Rx30[2])
13 DX Channel 3 SGD EOL Shadow............(Rx30[1])
12 DX Channel 3 SGD Flag Shadow.............(Rx30[0])
11 DX Channel 2 SGD Active Shadow .........(Rx20[7])
10 DX Channel 2 SGD Stop Shadow ............(Rx20[2])
9 DX Channel 2 SGD EOL Shadow............(Rx20[1])
8 DX Channel 2 SGD Flag Shadow.............(Rx20[0])
7 DX Channel 1 SGD Active Shadow .........(Rx10[7])
6 DX Channel 1 SGD Stop Shadow ............(Rx10[2])
5 DX Channel 1 SGD EOL Shadow............(Rx10[1])
4 DX Channel 1 SGD Flag Shadow.............(Rx10[0])
3 DX Channel 0 SGD Active Shadow .........(Rx00[7])
2 DX Channel 0 SGD Stop Shadow ............(Rx00[2])
1 DX Channel 0 SGD EOL Shadow............(Rx00[1])
0 DX Channel 0 SGD Flag Shadow.............(Rx00[0])
I/O Offset 8B-88 – Codec GPI Interrupt Status / GPIO.RO
This register may be accessed from either function 5 or 6
31-16 GPI Interrupt Status...........................................RO
R GPI[15-0] Interrupt Status
W 1 to clear
15-0 Codec GPIO.........................................................RO
R Reflect status of Codec GPI[15-0]
W Triggers AC-Link slot-12 output to codec
I/O Offset 8F-8C – Codec GPI Interrupt Enable............RO
This register may be accessed from either function 5 or 6
31-16 Interrupt on GPI[15-0] Change of Status..........RO
0 Disable
1 Enable
15-0 Reserved ........................................always reads 0
Offset 90-9F – Mapped from Function 5/6 Rx40-4F.......RO