Product specifications

VT8235 V-Link South Bridge
Revision 1.22 October 24, 2002 -99- Device 17 Function 1 Enhanced IDE Controller Registers
Offset 70 – Primary IDE Status ....................................... RO
7 Interrupt Status................................................... RO
1 Primary channel interrupt request pending
6 Prefetch Buffer Status ........................................ RO
1 PIO Prefetch transaction in progress
5 Post Write Buffer Status..................................... RO
1 PIO Post Write transaction in progress
4 DMA Read Prefetch Status................................ RO
1 DMA Read Prefetch transaction in progress
3 DMA Write Pipeline Status................................ RO
1 DMA Write transaction in progress
2 S/G Operation Complete .................................... RO
1 Scatter / Gather operation complete
1 FIFO Empty Status............................................. RO
1 Primary Channel FIFO empty
0 Response to External DMA Request ................. RO
1 External pri channel DMA request pending
Offset 71 – Primary Interrupt Control (01h)..................RW
7-1 Reserved ........................................ always reads 0
0 Interrupt Gating
0 Disable
1 Enable (IRQ output gated until FIFO empty)
....................................................default
Offset 78 – Secondary IDE Status.................................... RO
7 Interrupt Status................................................... RO
1 Secondary channel interrupt request pending
6 Prefetch Buffer Status ........................................ RO
1 PIO Prefetch transaction in progress
5 Post Write Buffer Status..................................... RO
1 PIO Post Write transaction in progress
4 DMA Read Prefetch Status................................ RO
1 DMA Read Prefetch transaction in progress
3 DMA Write Pipeline Status................................ RO
1 DMA Write transaction in progress
2 S/G Operation Complete .................................... RO
1 Scatter / Gather operation complete
1 FIFO Empty Status............................................. RO
1 Secondary Channel FIFO empty
0 Response to External DMA Request ................. RO
1 External sec channel DMA request pending
Offset 79 - Secondary Interrupt Control (01h)...............RW
7-1 Reserved ........................................ always reads 0
0 Interrupt Gating
0 Disable
1 Enable (IRQ output gated until FIFO empty)
....................................................default
Offset 83-80 – Primary S/G Descriptor Address ............ RO
Offset 8B-88 – Secondary S/G Descriptor Address ........ RO
These registers are used for debugging purposes only.
IDE Power Management Registers
Offset C3-C0 – Power Management Capabilities ...........RO
31-0 PCI PM Block 1 .................always reads 0002 0001h
This field reports support details for Power
Management Capabilities according to the PCI Power
Management specification.
Offset C7-C4 – Power State ..............................................RO
31-2 Reserved ........................................always reads 0
1-0 Power State
00 D0 .................................................... default
01 -reserved-
10 -reserved-
11 D3 Hot
IDE Back Door Registers
Offset D0 – Back Door – Revision ID (06h)....................RW
Offset D3-D2 – Back Door – Device ID (0571h)............. RW
Offset D5-D4 – Back Door – Sub-Vendor ID (0000h).... RW
Offset D7-D6 – Back Door – Sub-Device ID (0000h)..... RW
IDE Revision ID
Offset F6 – IDE New Revision ID (07h)...........................RO
IDE I/O Registers
These registers are compliant with the SFF 8038I v1.0
standard. Refer to the SFF 8038I v1.0 specification for further
details.
I/O Offset 0 - Primary Channel Command
I/O Offset 2 - Primary Channel Status
I/O Offset 4-7 - Primary Channel PRD Table Address
I/O Offset 8 - Secondary Channel Command
I/O Offset A - Secondary Channel Status
I/O Offset C-F - Secondary Channel PRD Table Address