Product specifications

VT8235 V-Link South Bridge
Revision 1.22 October 24, 2002 -98- Device 17 Function 1 Enhanced IDE Controller Registers
Offset 54 – UltraDMA FIFO Control (04h) ....................RW
7 Reserved ........................................ always reads 0
6 Lower ISA Request Priority When Write Device
Packet Command is Issued
The IDE secondary channel shares a bus internally
with the ISA interface. When this bit is enabled, the
IDE secondary channel is given higher priority over
ISA, which results in better performance.
0 Disable .................................................. default
1 Enable
5 Clear Native Mode Interrupt on Falling Edge of
Gated Interrupt
0 Disable .................................................. default
1 Enable. The interrupt will be automatically
cleared on the falling edge of the gated
interrupt.
4 Improve PIO Prefetch and Post-Write
Performance
0 Enable. PIO prefetch and post write
performance is increased by being given
higher throughput.................................. default
1 Disable
3 Memory Prefetch Size
This bit determines how many lines are prefetched
from memory for IDE transactions.
0 Prefetch 1 line ....................................... default
1 Prefetch 2 lines (16 DoubleWords). This
setting improves ATA100 throughput.
2 Change Drive Clears All FIFO & Internal States
0 Disable
1 Command switch from one drive to another
drive in the same channel terminates all
previous outstanding transactions involving
the previous drive..................................default
1 Reserved ........................................ always reads 0
0 Complete DMA Cycle with Transfer Size Less
Than FIFO Size
0 Enable. DMA transfer size is less than the
FIFO size............................................... default
1 Disable
Offset 55 – IDE Clock Gating (00h) ................................ RW
7-2 Reserved ........................................always reads 0
1 Dynamic 100 / 133 MHz Clock Gating
0 Enable....................................................default
1 Disable
0 Dynamic 66 MHz Clock Gating
0 Enable....................................................default
1 Disable
Offset 61-60 - Primary Sector Size (0200h) .................... RW
15-12 Reserved ........................................always reads 0
11-0 Number of Bytes Per Sector ...def=200h (512 bytes)
This field determines the maximum number of bytes
that can be prefetched when Rx44[4] = 1.
Offset 69-68 - Secondary Sector Size (0200h)................. RW
15-12 Reserved ........................................always reads 0
11-0 Number of Bytes Per Sector ...def=200h (512 bytes)
This field determines the maximum number of bytes
that can be prefetched when Rx44[4] = 1.