Product specifications

VT8235 V-Link South Bridge
Revision 1.22 October 24, 2002 -97- Device 17 Function 1 Enhanced IDE Controller Registers
Offset 4B-48 - Drive Timing Control (A8A8A8A8h)......RW
The following fields define the Active Pulse Width and
Recovery Time for the IDE DIOR# and DIOW# signals when
accessing the data ports (1F0 and 170):
One Completed Cycle
?]]]]]]]]]]]]"?
DIOR# / DIOW#
KIOOOOOUKKKKKKIO
Active Time Recovery Time
31-28 Primary Drive 0 Active Pulse Width...... def=1010b
27-24 Primary Drive 0 Recovery Time............. def=1000b
23-20 Primary Drive 1 Active Pulse Width...... def=1010b
19-16 Primary Drive 1 Recovery Time............. def=1000b
15-12 Secondary Drive 0 Active Pulse Width ..def=1010b
11-8 Secondary Drive 0 Recovery Time ......... def=1000b
7-4 Secondary Drive 1 Active Pulse Width .. def=1010b
3-0 Secondary Drive 1 Recovery Time .........def=1000b
The actual value for each field is the encoded value in the field
plus one and indicates the number of PCI clocks. For
example, if the value in the field is 1010b (10 decimal), the
active pulse width or recovery time is 11 PCI clocks.
Offset 4C - Address Setup Time (FFh)............................RW
The following fields define the Address Setup Time. The
Address Setup Time is measured from the point when address
signals are stable to the point when DIOR# and DIOW# are
asserted. The IDE specification requires the setup time to not
exceed 1T. However, the VT8233 provides flexibility for
devices that may not be able to meet the 1T requirement.
7-6 Primary Drive 0 Address Setup Time
5-4 Primary Drive 1 Address Setup Time
3-2 Secondary Drive 0 Address Setup Time
1-0 Secondary Drive 1 Address Setup Time
For each field above:
00 1T
01 2T
10 3T
11 4T ....................................................default
Offset 4E – Sec Non-1F0 Port Access Timing (B6h).......RW
7-4 DIOR# / DIOW# Active Pulse Width.......def = 0Bh
3-0 DIOR# / DIOW# Recovery Time.............. def = 06h
Offset 4F – Pri Non-1F0 Port Access Timing (B6h) .......RW
7-4 DIOR# / DIOW# Active Pulse Width.......def = 0Bh
3-0 DIOR# / DIOW# Recovery Time.............. def = 06h
The above fields define the primary and secondary channel
DIOR# and DIOW# active pulse widths and recovery times
when accessing non-data ports. The times are defined in terms
of PCI clocks and the actual value is equal to the value
encoded in the field plus one.
Offset 53-50 - UltraDMA Extended Timing Control..... RW
31 Pri Drive 0 UltraDMA-Mode Enable Method
0 Enable by using “Set Feature” command ....def
1 Enable by setting bit-30 of this register
30 Pri Drive 0 UltraDMA-Mode Enable
0 Disable...................................................default
1 Enable UltraDMA-Mode Operation
29 Pri Drive 0 Transfer Mode
0 DMA or PIO Mode ...............................default
1 UltraDMA Mode
28 Pri Drive 0 Cable Type Reporting
0 40-pin cable is being used......................default
1 80-pin cable is being used
27-24 Pri Drive 0 Cycle Time (T = 7.5 ns for 133 MHz)
0000 2T
0001 3T
0010 4T
0011 5T
0100 6T
0101 7T
0110 8T
0111 9T .............................default
1000 10T
1001 11T
1010 12T
1011 13T
1100 14T
1101 15T
1110 16T
1111 17T
23 Pri Drive 1 UltraDMA-Mode Enable Method
22 Pri Drive 1 UltraDMA-Mode Enable
21 Pri Drive 1 Transfer Mode
20 Pri Drive 1 Cable Type Reporting
0 40-pin cable is being used......................default
1 80-pin cable is being used
19-16 Pri Drive 1 Cycle Time....................default = 0111b
15 Sec Drive 0 UltraDMA-Mode Enable Method
14 Sec Drive 0 UltraDMA-Mode Enable
13 Sec Drive 0 Transfer Mode
12 Sec Drive 0 Cable Type Reporting
0 40-pin cable is being used......................default
1 80-pin cable is being used
11-8 Sec Drive 0 Cycle Time ..................default = 0111b
7 Sec Drive 1 UltraDMA-Mode Enable Method
6 Sec Drive 1 UltraDMA-Mode Enable
5 Sec Drive 1 Transfer Mode
4 Sec Drive 1 Cable Type Reporting
0 40-pin cable is being used......................default
1 80-pin cable is being used
3-0 Sec Drive 1 Cycle Time ..................default = 0111b
Each byte defines UltraDMA operation for the indicated drive.
The bit definitions are the same within each byte.