Product specifications

VT8235 V-Link South Bridge
Revision 1.22 October 24, 2002 -96- Device 17 Function 1 Enhanced IDE Controller Registers
Offset 44 - Miscellaneous Control 1 (08h).......................RW
7-5 Reserved ........................................ always reads 0
4 PIO Read Pre-Fetch Byte Counter
Determines whether the amount of data prefetched
under PIO read is limited.
0 Disable (no limit) .................................. default
1 Enable. The maximum number of bytes that
can be prefetched is determined by Rx61-
60[11:0] for the primary channel and Rx69-
68[11:0] for the secondary channel.
3 Bus Master IDE Status Register Read Retry
Determines whether a read to the bus master IDE
status register is retried when DMA operation is not
complete.
0 Disable. Reads will return status even if DMA
operation is not complete.
1 Enable. Reads of the status register are
automatically retried while DMA operation is
not complete..........................................default
2 Packet Command Prefetching
Determines whether prefetching is enabled for packet
commands. Packet commands are commands for
ATAPI, which is used for operating devices such as
CD-ROM drives.
0 Disable .................................................. default
1 Enable
1 Reserved ........................................ always reads 0
0 UltraDMA Host Must Wait for First Transfer
Before Termination
0 Enable. The UltraDMA host must wait until at
least the first transfer is completed before it
can terminate a transaction.................... default
1 Disable
Offset 45 - Miscellaneous Control 2 (20h)....................... RW
7 Reserved ........................................always reads 0
6 Interrupt Steering Swap
Controls whether primary and secondary channel
interrupts are swapped.
0 Primary channel interrupt is steered to IRQ14,
Secondary channel is steered to IRQ15 . default
1 Primary channel interrupt is steered to IRQ15,
Secondary channel interrupt steered to IRQ14
5 Reserved ...................................... always reads 1
4 Rx3C Write Protect
0 Disable (writes to Rx3C are allowed)....default
1 Enable (writes to Rx3C are ignored). Under
Native Mode (Rx9[2]=1 or Rx9[0]=1) Rx3C
should not be write protected as it is used to
route IRQ lines.
3 “Memory-Read-Multiple” Command
0 Disable...................................................default
1 Enable
2 “Memory-Write-and-Invalidate” Command
0 Disable...................................................default
1 Enable
1-0 Reserved ........................................always reads 0
Offset 46 - Miscellaneous Control 3 (C0h)...................... RW
7 Primary Channel Read DMA FIFO Flush
0 Disable
1 Enable. The primary channel DMA FIFO is
flushed when an interrupt request is generated
...................................................default
6 Secondary Channel Read DMA FIFO Flush
0 Disable
1 Enable. The secondary channel DMA FIFO is
flushed when an interrupt request is generated
...................................................default
5-0 Reserved ........................................always reads 0