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VT8235

V-LINK CLIENT

IGHLY INTEGRATED

OUTH BRIDGE

HIGH BANDWIDTH V-LINK CLIENT CONTROLLER

NTEGRATED FAST ETHERNET

NTEGRATED DIRECT SOUND AC97 AUDIO,

LTRADMA-133/100/66/33 MASTER MODE EIDE CONTROLLER,

IX PORT USB CONTROLLER FOR USB 2.0 AND USB 1.1,

EYBOARD / MOUSE CONTROLLER, RTC

LPC, SMB

US, SERIAL IRQ, PLUG AND PLAY, ACPI,

and PC2001 C

OMPLIANT Enhanced Power Management

Revision 1.22

October 24, 2002

VIA TECHNOLOGIES, INC.

Summary of content (145 pages)

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VT8235 V-LINK CLIENT HIGHLY INTEGRATED SOUTH BRIDGE HIGH BANDWIDTH V-LINK CLIENT CONTROLLER INTEGRATED FAST ETHERNET INTEGRATED DIRECT SOUND AC97 AUDIO, ULTRADMA-133/100/66/33 MASTER MODE EIDE CONTROLLER, SIX PORT USB CONTROLLER FOR USB 2.0 AND USB 1.1, KEYBOARD / MOUSE CONTROLLER, RTC LPC, SMBUS, SERIAL IRQ, PLUG AND PLAY, ACPI, and PC2001 COMPLIANT Enhanced Power Management Revision 1.22 October 24, 2002 VIA TECHNOLOGIES, INC.
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Copyright Notice: Copyright © 2002, VIA Technologies Incorporated. Printed in the United States. ALL RIGHTS RESERVED. No part of this document may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language, in any form or by any means, electronic, mechanical, magnetic, optical, chemical, manual or otherwise without the prior written permission of VIA Technologies Incorporated.
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW REVISION HISTORY Document Release 1.0 1.1 1.2 1.21 1.22 Date 7/22/02 Revision Initial external release (same as internal release 0.
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW TABLE OF CONTENTS REVISION HISTORY....................................................................................................................................................................... I TABLE OF CONTENTS.................................................................................................................................................................. II LIST OF FIGURES .................................................
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW SMB GPIO Slave Command Codes...................................................................................................................................................... 79 General Purpose I/O Control Registers ................................................................................................................................................. 80 Power Management I/O-Space Registers ..............................................
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW LIST OF FIGURES FIGURE 1. FIGURE 2. FIGURE 3. FIGURE 4. FIGURE 5. PC SYSTEM CONFIGURATION USING THE VT8235......................................................................................... 5 VT8235 BALL DIAGRAM (TOP VIEW) .................................................................................................................. 6 POWER MANAGEMENT SUBSYSTEM BLOCK DIAGRAM ................................................................
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW VT8235 LOW COST V-LINK CLIENT HIGHLY INTEGRATED SOUTH BRIDGE HIGH BANDWIDTH V-LINK CLIENT CONTROLLER INTEGRATED FAST ETHERNET, INTEGRATED DIRECT SOUND AC97 AUDIO, ULTRADMA-133/100/66/33 MASTER MODE EIDE CONTROLLER, SIX PORT USB 2.
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW x Concurrent PCI Bus Controller − 33 MHz operation − Supports up to six PCI masters − Peer concurrency − Concurrent multiple PCI master transactions; i.e.
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW x System Management Bus Interface − Host interface for processor communications − Slave interface for external SMBus masters x Universal Serial Bus Controller − USB v2.0 and Enhanced Host Controller Interface (EHCI) v1.0 compatible − USB v1.1 and Universal Host Controller Interface (UHCI) v1.
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW OVERVIEW The VT8235 South Bridge is a high integration, high performance, power-efficient, and high compatibility device that supports Intel and non-Intel based processor to V-Link bus bridge functionality to make a complete Microsoft PC2001-compliant PCI/LPC system. The VT8235 includes standard intelligent peripheral controllers: a) IEEE 802.3 compliant 10 / 100 Mbps PCI bus master Ethernet MAC with standard MII interface to external PHYceiver.
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW CA CD CPU / Cache Sideband Signals: Init / A20M# INTR / NMI SMI / StopClk FERR / IGNNE Sleep North Bridge MA/Command MD Vlink Interface System Memory DIMM Module ID SMB USB 2.0 Ports 0-5 Keyboard / Mouse LPC VT8235 Boot ROM Expansion Cards PCI 487 BGA IDE Primary and Secondary Onboard LPC I/O AC97 Link APIC GPIO, Power Control, Reset MII Fast Ethernet Interface RTC Crystal Figure 1.
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW PINOUTS Key 1 Figure 2.
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW Table 1.
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW Table 2.
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW PIN DESCRIPTIONS Table 3. Pin Descriptions V-Link Interface Signal Name VAD[15:0] Pin # I/O Signal Description K22, J22, G24, H22, G22, G23, F23, D25, K26, K24, E24, E26, J25, J26, F26, F25 D26 VPAR VBE[1:0]# L26, F24 VCLK UPCMD DNCMD UPSTB UPSTB# DNSTB DNSTB# VLVREF VLCOMP VCCVK L24 K25 J24 H24 H26 G25 G26 J23 K23 (see pin list) IO Address / Data Bus. Bits 0-7 are implemented and bits 8-15 are reserved for future use.
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW CPU Interface Signal Name Pin # I/O Signal Description OD A20 Mask. Connect to A20 mask input of the CPU to control address bit-20 generation. Logical combination of the A20GATE input (from internal or external keyboard controller) and Port 92 bit-1 (Fast_A20). U26 I Numerical Coprocessor Error. This signal is tied to the coprocessor error signal on the FERR# CPU. Internally generates interrupt 13 if active.
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW PCI Bus Interface Signal Name Pin # DEVSEL# (see pin list) L1, A4, D1, F4 B3 FRAME# B4 IRDY# TRDY# STOP# SERR# C4 A3 C3 C1 PAR INTA# INTB# INTC# INTD# INTE# / GPIO12 / PCGNTA, INTF# / GPIO13 / PCGNTB, INTG# / GPIO14, INTH# / GPIO15 REQ5# / GPI7, REQ4#, REQ3#, REQ2#, REQ1#, REQ0# GNT5# / GPO7, GNT4#, GNT3#, GNT2#, GNT1#, GNT0# PCIRST# PCICLK PCKRUN# D3 P1, P2, P3, R1 AD[31:0] CBE[3:0]# A7, B8, D8, C7 N4 L4 H4 D4 C5 D6 P4 M4 J4 E4 D5 E6 R2
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW LAN Controller - Media Independent Interface (MII) Signal Name Pin # I/O MCOL MCRS C13 B13 I I MDCK C9 O MDIO B9 IO B10 A9, D9, D10, E10 I I MRXDV MRXERR C10 A10 I I MTXCLK A12 I MTXD[3-0] C11, B11, A11, C12 O MTXENA B12 O MIIVCC MIIVCC25 RAMVCC RAMGND D11, D12, E11, E12 D13, E13 E7 E8 Power Power Power Power MRXCLK MRXD[3-0] PU Signal Description PD MII Collision Detect. From the external PHY. PD MII Carrier Sense.
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW Universal Serial Bus 2.
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW UltraDMA-133 / 100 / 66 / 33 Enhanced IDE Interface Signal Name Pin # I/O PDRDY / PDDMARDY / PDSTROBE Y26 I SDRDY / SDDMARDY / SDSTROBE AD15 I PDIOR# / PHDMARDY / PHSTROBE Y24 O SDIOR# / SHDMARDY / SHSTROBE AF22 O PDIOW# / PSTOP Y25 O SDIOW# / SSTOP AC21 O PDDRQ SDDRQ PDDACK# SDDACK# IRQ14 IRQ15 Y22 AE15 W26 AD22 AE24 AF24 I I O O I I Revision 1.22 October 24, 2002 Signal Description EIDE Mode: Primary I/O Channel Ready.
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW UltraDMA-133 / 100 / 66 / 33 Enhanced IDE Interface (continued) Signal Name Pin # I/O PDCS1# V24 O PDCS3# W24 SDCS1# / strap AC23 SDCS3# / strap AD23 PDA[2-0] SDA[2-0] / strap PDD[15-0] SDD[15-0] / SA[15-0] PDCOMP SDCOMP V26, V25, Y23 AF23, AC22, AE23 (see pin list) (see pin list) W23 AC15 Signal Description Primary Master Chip Select. This signal corresponds to CS1FX# on the primary IDE connector. O Primary Slave Chip Select.
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW Internal Keyboard Controller Signal Name MSCK / IRQ1 Pin # I/O PU W2 IO / I PU Signal Description MultiFunction Pin (Internal mouse controller enabled by Rx51[1]) Rx51[2]=1 Mouse Clock. From internal mouse controller. Rx51[2]=0 Interrupt Request 1. Interrupt input 1. MSDT / IRQ12 W1 IO / I PU MultiFunction Pin (Internal mouse controller enabled by Rx51[1]) Rx51[2]=1 Mouse Data. From internal mouse controller. Rx51[2]=0 Interrupt Request 12.
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW General Purpose Inputs Signal Name Pin # General Purpose Input 0. Status on PMIO Rx20[0] General Purpose Input 1. Status on PMIO Rx20[1] General Purpose Input 2. Status on PMIO Rx20[4] General Purpose Input 3. Status on PMIO Rx20[8] General Purpose Input 4. Status on PMIO Rx20[11] General Purpose Input 5. Status on PMIO Rx20[12] General Purpose Input 6. Status on PMIO Rx20[5] General Purpose Input 7. RxE4[2] = 0 General Purpose Input 8.
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW General Purpose I/O Signal Name Pin # I/O Signal Description GPIOA / GPI24 / GPO24 AE5 IO General Purpose I/O A / 24. RxE6[0] = 1 GPIOC / GPI25 / GPO25 AE6 IO General Purpose I/O C / 25. GPIOD / GPI30 / GPO30 AD6 IO General Purpose I/O D / 30. GPIOE / GPI31 / GPO31 AC6 IO General Purpose I/O E / 31.
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW Power Management and Event Detection Signal Name Pin # I/O Signal Description PWRBTN# AD2 SLPBTN# / GPIO21 / ACSDIN3 / PCS1# RSMRST# EXTSMI# / GPI2 PME# SMBALRT# LID# / GPI4 INTRUDER# / GPI16 THRM# / GPI18 / AOLGPI RING# / GPI3 BATLOW# / GPI5 CPUSTP# / GPO5 PCISTP# / GPO6 SUSA# / GPO1 SUSB# / GPO2 SUSC# SUSST1# / GPO3 SUSCLK CPUMISS / GPI17 AOLGPI / GPI18 / THRM# Power Button.
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW Resets, Clocks, and Power Status Signal Name Pin # I/O PWRGD AF4 I PWROK# PCIRST# AE2 R2 O O OSC RTCX1 AC12 AD4 I I RTCX2 TEST TPO AF3 AF9 U24 O I O Signal Description Power Good. Connected to the Power Good signal on the Power Supply. Internal logic powered by VBAT. Power OK. Internal logic powered by VSUS33. PCI Reset. Active low reset signal for the PCI bus.
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW REGISTERS Register Overview Table 6. System I/O Map The following tables summarize the configuration and I/O registers of the VT8235. These tables also document the power-on default value (“Default”) and access type (“Acc”) for each register. Access type definitions used are RW (Read/Write), RO (Read/Only), “—” for reserved / used (essentially the same as RO), and RWC (or just WC) (Read / Write 1’s to Clear individual bits).
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW Table 7.
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW Keyyboard / Mouse Wakeup Registers (I/O Space) Memory Mapped Registers – IOAPIC Default Acc Port KB / Mouse Wakeup Registers 002E Keyboard / Mouse Wakeup Index † 00 RW 002F Keyboard / Mouse Wakeup Data † 00 RW † Keyboard / Mouse Wakeup registers (index values E0-EF defined below) are accessible if Function 0 PCI Configuration register Rx51[1] = 1.
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW Device 16 Function 0 Registers – USB 1.
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW Device 16 Function 1 Registers – USB 1.
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW Device 16 Function 2 Registers – USB 1.
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW Device 16 Function 3 Registers – USB 2.
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW Device 17 Function 0 Registers – Bus Control & Power Management Configuration Space Bus Control & PM Header Registers Offset 1-0 3-2 5-4 7-6 8 9 A B C D E F 10-27 28-2B 2D-2C 2F-2E 30-33 34-3B 3C 3D 3E 3F Configuration Space Header Vendor ID Device ID Command Status Revision ID Programming Interface Sub Class Code Base Class Code -reserved- (cache line size) -reserved- (latency timer) Header Type Built In Self Test (BIST) -reserved- (base address
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW Configuration Space Power Management Registers Offset 80 81 82 83 85-84 87-86 8B-88 8C 8D 8E-8F 93-90 94 95 96 97 98 99 9A 9B-A0 A1 A2 A3 A4-BF C3-C0 C7-C4 C8-CF Power Management General Configuration 0 General Configuration 1 ACPI Interrupt Select -reservedPrimary Interrupt Channel Secondary Interrupt Channel Power Mgmt I/O Base (256 Bytes) Host Bus Power Mgmt Control Throttle / Clock Stop Control -reservedGP Timer Control Power Well Control Misc
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW I/O Space Power Management Registers I/O Space System Management Bus Registers Offset 1-0 3-2 5-4 6-7 B-8 C-F Basic Control / Status Registers Power Management Status Power Management Enable Power Management Control -reservedPower Management Timer -reserved- Default 0000 0000 0000 00 0000 0000 00 Acc WC RW RW — RW — Offset 13-10 14 15 16-1F Processor Registers Processor and PCI Bus Control Processor LVL2 Processor LVL3 -reserved- Default 00
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW Device 17 Function 1 Registers – IDE Controller Configuration Space IDE Header Registers Offset Configuration Space Header 1-0 Vendor ID 3-2 Device ID 5-4 Command 7-6 Status 8 Revision ID 9 Programming Interface A Sub Class Code B Base Class Code C-F -reserved13-10 Base Address – Pri Data / Command 17-14 Base Address – Pri Control / Status 1B-18 Base Address – Sec Data / Command 1F-1C Base Address – Sec Control / Status 23-20 Base Address – Bus Mas
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW Device 17 Function 5 & 6 Registers – AC/MC97 Codecs Function 5 Configuration Space AC97 Header Registers Offset 1-0 3-2 5-4 7-6 8 9 A B C-F 13-10 17-14 1B-18 1F-1C 23-20 27-24 28-29 2F-2C 33-30 34 35-3B 3C 3D 3E 3F Configuration Space Header Vendor ID Device ID Command Status Revision ID Programming Interface Sub Class Code Base Class Code -reservedBase Address 0 - SGD Control/Status Base Address 1 (reserved) Base Address 2 (reserved) Base Address
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW Function 5 I/O Base 0 Registers – AC97 Audio S/G DMA 7B-78 7F-7C AC97 SGD I/O Registers SGD Channel x Status SGD Channel x Control SGD Channel x Left Volume SGD Channel x Right Volume SGD Channel x Table Pointer Base SGD Channel x Current Address Stop Index / Data Type / Sample Rate SGD Channel x Current Count SGD 3D Channel Status SGD 3D Channel Control SGD 3D Channel Format SGD 3D Channel Scratch SGD 3D Channel Table Pointer Base SGD 3D Channel
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW Device 18 Function 0 Registers - LAN Configuration Space LAN Header Registers Default Offset Configuration Space Header 1-0 Vendor ID 1106 3-2 Device ID 3065 5-4 Command 0000 7-6 Status 0470 8 Revision ID 40 9 Programming Interface 00 A Sub Class Code 00 B Base Class Code 00 C Cache Line Size 00 D Latency Timer 00 E Header Type 00 F BIST 00 13-10 I/O Base Address 0000 0000 17-14 Memory Base Address 0000 0000 18-27 -reserved00 2B-28 Card Bus CIS Poi
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW I/O Space LAN Registers Offset Power Management 5-0 Ethernet Address 6 Receive Control 7 Transmit Control 8 Command 0 9 Command 1 A-B -reservedC Interrupt Status 0 D Interrupt Status 1 E Interrupt Mask 0 F Interrupt Mask 1 17-10 Multicast Address 1B-18 Receive Address 1F-1C Transmit Address 23-20 Receive Status 27-24 Receive Data Buffer Control 2B-28 Receive Data Buffer Start Address 2F-2C Receive Data Buffer Branch Address 30-3F -reserved43-40 Tra
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW Register Descriptions Port 61 - Misc Functions & Speaker Control ................. RW 7-6 Reserved ........................................always reads 0 5 Timer/Counter 2 Output......................................RO This bit reflects the output of Timer/Counter 2 without any synchronization. 4 Refresh Detected...................................................RO This bit toggles on every rising edge of the ISA bus REFRESH# signal.
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW Port 60 - Keyboard Controller Input Buffer .................. WO Only write to port 60h if port 64h bit-1 = 0 (1=full). Keyboard Controller I/O Registers The keyboard controller handles the keyboard and mouse interfaces. Two ports are used: port 60 and port 64. Reads from port 64 return a status byte. Writes to port 64h are command codes (see command code list following the register descriptions). Input and output data is transferred via port 60.
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW Port 64 - Keyboard / Mouse Command.......................... WO This port is used to send commands to the keyboard / mouse controller. The command codes recognized by the VT8235 are listed in the table below. Table 8.
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW DMA Controller I/O Registers Ports 80-8F - DMA Page Registers There are eight DMA Page Registers, one for each DMA channel. These registers provide bits 16-23 of the 24-bit address for each DMA channel (bits 0-15 are stored in registers in the Master and Slave DMA Controllers). They are located at the following I/O Port addresses: Ports 00-0F - Master DMA Controller Channels 0-3 of the Master DMA Controller control System DMA Channels 0-3.
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW Interrupt Controller Shadow Registers Interrupt Controller I/O Registers The following shadow registers are enabled by setting function 0 Rx47[4]. If the shadow registers are enabled, they are read back at the indicated I/O port instead of the standard interrupt controller registers (writes are unchanged). Ports 20-21 - Master Interrupt Controller The Master Interrupt Controller controls system interrupt channels 0-7.
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW Offset 00 01 02 03 04 CMOS / RTC I/O Registers Port 70 - CMOS Address ..................................................RW 7 NMI Disable......................................................... RW 0 Enable NMI Generation. NMI is asserted on encountering SERR# on the PCI bus. 1 Disable NMI Generation ....................... default 6-0 CMOS Address (lower 128 bytes)....................... RW 05 Port 71 - CMOS Data.................................
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW Keyboard / Mouse Wakeup Index / Data Registers Index E1 – Keyboard Wakeup Scan Code Set 0 (F0h) .. RW 7-0 Keyboard Wakeup First Scan Code .........def = F0h Index E2 – Keyboard Wakeup Scan Code Set 1 (00h) .. RW 7-0 Keyboard Wakeup Second Scan Code .....def = 00h Index E3 – Keyboard Wakeup Scan Code Set 2 (00h) .. RW 7-0 Keyboard Wakeup Third Scan Code........def = 00h Index E4 – Keyboard Wakeup Scan Code Set 3 (00h) ..
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW Memory Mapped I/O APIC Registers Indexed I/O APIC Registers Memory Address FEC00000 – APIC Index ....................RW 7-0 APIC Index .......................................... default = 00h 8-bit pointer to APIC registers. Offset 0 – APIC Identification (0000 0000h) .................. RW 31-28 Reserved ........................................always reads 0 27-24 APIC Identification ..................................
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW Offset 3F-10 – I/O Redirection Table This table contains 24 registers, with one dedicated table entry for each of the 24 APIC interrupt signals. Each 64-bit register consists of two 32-bit values at consecutive index locations, with the low 32 bits at the even index and the upper 32 bits at the odd index. The default value for all registers is xxx1 xxxx xxxx xxxxh.
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW Configuration Space I/O There are 8 “functions” implemented in the VT8235 (see Table 5 on page 21). The following sections describe the registers and register bits of these functions. Configuration space accesses for all functions use PCI configuration mechanism 1 (see PCI specification revision 2.2 for more details). The ports respond only to double-word accesses. Byte or word accesses will be passed on unchanged.
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW Offset 8 - Revision ID (nnh) .............................................. RO 7-0 Silicon Revision Code (0 indicates first silicon) Device 16 Function 0 Registers - USB 1.1 UHCI Ports 0-1 This Universal Serial Bus host controller interface is fully compatible with UHCI specification v1.1. There are two sets of software accessible registers: PCI configuration registers and USB I/O registers.
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW USB-Specific Configuration Registers Offset 41 - Miscellaneous Control 2 (10h)....................... RW 7 USB 1.1 Improvement for EOP This bit controls whether USB Specification 1.1 or 1.0 is followed when a stuffing error occurs before an EOP (End-Of-Packet). A stuffing error results when the receiver sees seven consecutive ones in a packet. Under USB specification 1.
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW Offset 49 - Miscellaneous Control 6 (03h)....................... RW 7-6 Reserved ........................................always reads 0 5-4 Reserved (Do Not Program) ....................default = 0 3-2 Reserved ........................................always reads 0 1 EHCI Supports PME Assertion in D3 Cold State 0 Not Supported 1 Supported..............................................
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW USB I/O Registers These registers are compliant with the UHCI v1.1 standard. Refer to the UHCI v1.1 specification for further details. I/O Offset 1-0 - USB Command I/O Offset 3-2 - USB Status I/O Offset 5-4 - USB Interrupt Enable I/O Offset 7-6 - Frame Number I/O Offset B-8 - Frame List Base Address I/O Offset 0C - Start Of Frame Modify I/O Offset 11-10 - Port 0 Status / Control I/O Offset 13-12 - Port 1 Status / Control Revision 1.
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW Offset 8 - Revision ID (nnh) .............................................. RO 7-0 Silicon Revision Code (0 indicates first silicon) Device 16 Function 1 Registers - USB 1.1 UHCI Ports 2-3 This Universal Serial Bus host controller interface is fully compatible with UHCI specification v1.1. There are two sets of software accessible registers: PCI configuration registers and USB I/O registers.
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW USB-Specific Configuration Registers Offset 41 - Miscellaneous Control 2 (10h)....................... RW 7 USB 1.1 Improvement for EOP This bit controls whether USB Specification 1.1 or 1.0 is followed when a stuffing error occurs before an EOP (End-Of-Packet). A stuffing error results when the receiver sees seven consecutive ones in a packet. Under USB specification 1.
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW Offset 49 - Miscellaneous Control 6 (03h)....................... RW 7-6 Reserved ........................................always reads 0 5-4 Reserved (Do Not Program) ....................default = 0 3-2 Reserved ........................................always reads 0 1 EHCI Supports PME Assertion in D3 Cold State 0 Not Supported 1 Supported..............................................
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW USB I/O Registers These registers are compliant with the UHCI v1.1 standard. Refer to the UHCI v1.1 specification for further details. I/O Offset 1-0 - USB Command I/O Offset 3-2 - USB Status I/O Offset 5-4 - USB Interrupt Enable I/O Offset 7-6 - Frame Number I/O Offset B-8 - Frame List Base Address I/O Offset 0C - Start Of Frame Modify I/O Offset 11-10 - Port 0 Status / Control I/O Offset 13-12 - Port 1 Status / Control Revision 1.
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW Offset 8 - Revision ID (nnh) .............................................. RO 7-0 Silicon Revision Code (0 indicates first silicon) Device 16 Function 2 Registers - USB 1.1 UHCI Ports 4-5 This Universal Serial Bus host controller interface is fully compatible with UHCI specification v1.1. There are two sets of software accessible registers: PCI configuration registers and USB I/O registers.
PAGE 61
VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW USB-Specific Configuration Registers Offset 41 - Miscellaneous Control 2 (10h)....................... RW 7 USB 1.1 Improvement for EOP This bit controls whether USB Specification 1.1 or 1.0 is followed when a stuffing error occurs before an EOP (End-Of-Packet). A stuffing error results when the receiver sees seven consecutive ones in a packet. Under USB specification 1.
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW Offset 49 - Miscellaneous Control 6 (03h)....................... RW 7-6 Reserved ........................................always reads 0 5-4 Reserved (Do Not Program) ....................default = 0 3-2 Reserved ........................................always reads 0 1 EHCI Supports PME Assertion in D3 Cold State 0 Not Supported 1 Supported..............................................
PAGE 63
VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW USB I/O Registers These registers are compliant with the UHCI v1.1 standard. Refer to the UHCI v1.1 specification for further details. I/O Offset 1-0 - USB Command I/O Offset 3-2 - USB Status I/O Offset 5-4 - USB Interrupt Enable I/O Offset 7-6 - Frame Number I/O Offset B-8 - Frame List Base Address I/O Offset 0C - Start Of Frame Modify I/O Offset 11-10 - Port 0 Status / Control I/O Offset 13-12 - Port 1 Status / Control Revision 1.
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW Device 16 Function 3 Registers - USB 2.0 EHCI Offset 9 - Programming Interface (20h) .......................... RO Offset A - Sub Class Code (03h=USB Controller) .......... RO Offset B - Base Class Code (0Ch=Serial Bus Controller)RO This Enhanced Serial Bus host controller interface is fully compatible with EHCI specification v1.0. There are two sets of software accessible registers: PCI configuration registers and USB I/O registers.
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW USB-Specific Configuration Registers Offset 60 - Serial Bus Release Number (20h) .................. RO 7-0 Release Number..........always reads 20h for USB 2.0 Offset 40 - Miscellaneous Control 1 (40h) .......................RW 7 Reserved ........................................ always reads 0 6 Babble Option This bit controls whether the port is disabled when EOF (End-Of-Frame) babble occurs.
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW EHCI USB 2.0 I/O Registers These registers are compliant with the EHCI v1.0 standard. Refer to the EHCI v1.0 specification for further details. EHCI Capabilities I/O Offset 0 - Capability Register Length (10h) I/O Offset 3-2 - Interface Version Number (0100h) ......RO† I/O Offset 7-4 – Structure Parameters (0000 3206h) ....RO† I/O Offset B-8 – Capability Parameters (0000 6872h) .RO† † RW if Rx42[4] = 1.
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW Device 17 Function 0 Registers – Bus Control and Power Management All registers are located in the device 17 function 0 configuration space of the VT8235. These registers are accessed through PCI configuration mechanism #1 via I/O address 0CF8h / 0CFCh. PCI Configuration Space Header Offset 8 - Revision ID (nnh) .............................................. RO 7-0 Revision ID Offset 1-0 - Vendor ID (1106h).........................................
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW ISA Bus Control Offset 40 - ISA Bus Control (00h) ....................................RW 7 ISA Command Delay 0 Normal .................................................. default 1 Extra 6 I/O Recovery Time The number of clocks between 2 I/O commands 0 Disable .................................................. default 1 Enable (Rx4C[7:6] determines the # of clocks) 5 ROM Wait States 0 1 Wait State ...........................................
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW Offset 49 – CCA Control.................................................. RW 7 Reserved ........................................always reads 0 6 South Bridge Internal Master Devices Priority Higher Than External PCI Master 0 Disable ................................................... default 1 Enable The “CCA” is an internal arbiter that controls the priority of external PCI masters vs. internal master devices.
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW Miscellaneous Control Offset 4C - IDE Interrupt Routing (04h) ........................RW 7-6 I/O Recovery Time Select When Rx40[6] is enabled, this field determines the I/O recovery time. 00 1 Bus Clock ........................................... default 01 2 Bus Clock 10 4 Bus Clock 11 8 Bus Clock 5-4 Reserved (do not program) ..................... default = 0 3-2 IDE Secondary Channel IRQ Routing 00 IRQ14 01 IRQ15.................................
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW Function Control Offset 51 – Function Control 2 (0Dh).............................. RW 7-6 Reserved ........................................always reads 0 5 Internal LAN Controller Clock Gating When bit-4 of this register is disabled, the LAN function is disabled but the LAN controller clock is not gated automatically. This bit controls whether the clock is actually gated. 0 Disable ...................................................
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW Serial IRQ, LPC, and PC/PCI DMA Control Plug and Play Control - PCI Offset 52 – Serial IRQ & LPC Control (00h)..................RW 7 Reserved ........................................ always reads 0 6 LPC Short Wait Abort 0 Disable .................................................. default 1 Enable. During a short wait, the cycle is aborted after 8Ts. 5 LPC Frame Wait State Time 0 Frame Wait State is 1T..........................
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW GPIO and Miscellaneous Control Offset 59 – Miscellaneous Control 1 (00h) ...................... RW 7-6 Reserved ........................................always reads 0 5 LPC RTC 0 Disable ................................................... default 1 Enable 4 LPC Keyboard 0 Disable (ISA Keyboard) ........................
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW Offset 5B – Miscellaneous Control 2 (01h) ..................... RW 7-4 Reserved ........................................always reads 0 3 Bypass APIC De-Assert Message 0 Disable ................................................... default 1 Enable 2 APIC HyperTransport Mode 0 Disable ................................................... default 1 Enable 1 INTE#, INTF#, INTG#, INTH# (pins GPIO12-15) 0 Disable ............................................
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW Programmable Chip Select Control Offset 66 – PCS Control (00h) ......................................... RW 7 PCS 3 Internal I/O 0 Disable (External) .................................. default 1 Enable (Internal) 6 PCS 2 Internal I/O 0 Disable (External) .................................. default 1 Enable (Internal) 5 PCS 1 Internal I/O 0 Disable (External) ..................................
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW ISA Decoding Control Offset 6C – ISA Positive Decoding Control 1..................RW 7 On-Board I/O (Ports 00-FFh) Positive Decoding 0 Disable .................................................. default 1 Enable 6 Microsoft-Sound System I/O Port Positive Decoding 0 Disable .................................................. default 1 Enable (bits 5-4 determine the decode range) 5-4 Microsoft Sound System I/O Decode Range 00 0530h-0537h ..............
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW I/O Pad Control Offset 7C – I/O Pad Control (00h) ...................................RW 7-6 Reserved ........................................ always reads 0 5-4 IDE Interface Output Drive Strength 00 Lowest ................................................... default … … 11 Highest 3-2 PLL PCLK Input Delay Select 00 .................................................... default … … 11 1-0 PLL CLK66 Feedback Delay Select 00 ............................
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW Power Management-Specific Configuration Registers Offset 81 - General Configuration 1 (04h) ...................... RW 7 I/O Enable for ACPI I/O Base 0 Disable access to ACPI I/O block.......... default 1 Allow access to Power Management I/O Register Block (see offset 4B-48 to set the base address for this register block).
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW Offset 82 - ACPI Interrupt Select ....................................RW 7 ATX / AT Power Indicator................................. RO 0 ATX 1 AT 6 PSON (SUSC#) Gating ....................................... RO During system on/off, this status bit reports whether PSON gating state has been completed, 0 meaning that gating is active now and 1 meaning that gating is complete.
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW Offset 87-86 - Secondary Interrupt Channel (0000h) .... RW For legacy PMU, the bits in this register are used in conjunction with: Offset 85-84 - Primary Interrupt Channel (0000h) ........RW If a device IRQ is enabled as a Primary IRQ, that device’s IRQ can be used to generate wake events.
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW Offset 8D – Throttle / Clock Stop Control...................... RW 7 Throttle Timer Reset......................................def = 0 6-5 Throttle Timer This field determines the number of bits used for the throttle timer, which in conjunction with the throttle timer tick determines the cycle time of STPCLK#. For example, if a 2-bit timer and a 7.5 usec timer tick are selected, the STPCLK# cycle time would be 30 usec (2**2 x 7.5).
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW Offset 93-90 - GP Timer Control (0000 0000h)...............RW 31-30 Conserve Mode Timer Count Value 00 1/16 second............................................ default 01 1/8 second 10 1 second 11 1 minute 29 Conserve Mode Status This bit reads 1 when in Conserve Mode 28 Conserve Mode This bit controls whether conserve mode (throttling) is enabled.
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW Offset 95 – Miscellaneous Power Well Control .............. RW 7 CPUSTP# to SUSST# Delay Select This bit controls the delay between the deassertion of CPUSTP# and the deassertion of SUSST# during a resume. 0 1 msec minimum ................................... default 1 125 usec minimum 6 SUSST# Deasserted Before PWRGD for STD 0 Disable ...................................................
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW Offset 99 – GP2 Timer...................................................... RW 7 Write: GP2 Timer Load Value...............default = 0 Read: GP2 Timer Current Count Offset 98 – GP2 / GP3 Timer Control .............................RW 7 GP3 Timer Start On setting this bit to 1, the GP3 timer loads the value defined by Rx5A and starts counting down.
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW System Management Bus-Specific Configuration Registers SMB GPIO Slave Command Codes Offset D1-D0 – SMBus I/O Base ......................................RW 15-4 I/O Base (16-byte I/O space) ............... default = 00h 3-0 Fixed ................................ always reads 0001b SMBus Command Code 0 – GPIO Slave Input Port ...... RO 7-0 Input Data ......................................
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW General Purpose I/O Control Registers Offset E5 – GPIO I/O Select 1 ......................................... RW 7 Voltage Regulator Change Timer Select 0 100 usec ................................................. default 1 200 usec 6 AGPBZ# Source of Bus Master Status 0 Disable ................................................... default 1 Enable 5 Reserved ........................................
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW Power Management I/O-Space Registers Basic Power Management Control and Status I/O Offset 3-2 - Power Management Enable .................. RW The bits in this register correspond to the bits in the Power Management Status Register at offset 1-0. I/O Offset 1-0 - Power Management Status .................RWC The bits in this register are set only by hardware and can be reset by software by writing a one to the desired bit position.
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW I/O Offset 5-4 - Power Management Control..................RW 15 Soft Resume This bit is used to allow a system using an AT power supply to operate as if an ATX power supply were being used. Refer to the BIOS Porting Guide for implementation details. 0 Disable .................................................. default 1 Enable 14 Reserved ........................................ always reads 0 13 Sleep Enable .................................
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW Processor Power Management Registers I/O Offset 13-10 - Processor & PCI Bus Control............RW 31-12 Reserved ........................................ always reads 0 11 Disable PCISTP# When PCKRUN# is Deasserted 0 Enable.................................................... default 1 Disable 10 PCI Bus Clock Run Without Stop 0 PCKRUN# is always asserted ...............
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW General Purpose Power Management Registers I/O Offset 23-22 - General Purpose SCI Enable ............ RW 15 Enable SCI on setting of Rx21-20[15].............def=0 14 Enable SCI on setting of Rx21-20[14].............def=0 13 Enable SCI on setting of Rx21-20[13].............def=0 12 Enable SCI on setting of Rx21-20[12].............def=0 11 Enable SCI on setting of Rx21-20[11].............def=0 10 Enable SCI on setting of Rx21-20[10].............
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW Generic Power Management Registers I/O Offset 2B-2A - Global Enable ................................... RW 15 GPIO Range 1 SMI Enable .....................default = 0 14 GPIO Range 0 SMI Enable .....................default = 0 13 GP3 Timer Timeout SMI Enable ............default = 0 12 GP2 Timer Timeout SMI Enable ............default = 0 11 SERIRQ SMI Enable ...............................default = 0 10 SMI on Sleep Enable Write ....................
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW I/O Offset 2F - SMI Command ........................................ RW 7-0 SMI Command Writing to this port sets the Software SMI Status bit. Note that if the Software SMI Enable bit is set (see Global Enable register Rx2A[6]), then an SMI is generated. I/O Offset 2D-2C - Global Control...................................RW 15-12 Reserved ........................................ always reads 0 11 IDE Secondary Bus Power-Off 0 Disable .............
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW I/O Offset 33-30 - Primary Activity Detect Status.......RWC These bits correspond to the Primary Activity Detect Enable bits in Rx37-34. If the corresponding bit is set in that register, setting of a bit below will cause the Primary Activity Status (PACT_STS) bit to be set (Global Status register Rx28[0]). All bits in this register default to 0, are set by hardware only, and may only be cleared by writing 1s to the desired bit.
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW I/O Offset 40 – Extended I/O Trap Status ................... RWC 7-5 Reserved ........................................always reads 0 4 BIOS Write Access Status 3 GP3 Timer Second Timeout With No Cycles 0 Disable ...................................................
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW General Purpose I/O Registers I/O Trap Registers I/O Offset 45 – SMI / IRQ / Resume Status .................... RO 7-5 Reserved ........................................ always reads 0 4 Latest PCSn Status 0 Latest PCSn was an I/O Read 1 Latest PCSn was an I/O Write 3 Serial SMI Status This bit is used to report a Serial-IRQ-generated SMI. 2 Reserved ........................................
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW System Management Bus I/O-Space Registers The base address for these registers is defined in RxD1-D0 of the Device 17 Function 0 PCI configuration registers. The System Management Bus I/O space is enabled for access by the system if Device 17 Function 0 RxD2[0] = 1. I/O Offset 01h – SMBus Slave Status........................... RWC 7-6 Reserved ........................................always reads 0 5 Alert Status ...................................
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW I/O Offset 03h – SMBus Host Command........................ RW 7-0 SMBUS Host Command ..........................default = 0 This field contains the data transmitted in the command field of the SMBus host transaction. I/O Offset 02h – SMBus Host Control.............................RW 7 Reserved ........................................ always reads 0 6 Start ........................................ always reads 0 0 Writing 0 has no effect ..........
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW I/O Offset 0B-0Ah – SMBus Slave Event........................ RW This register is used to enable generation of interrupt or resume events for accesses to the host controller’s slave port. 15-0 SMBus Slave Event ..................................default = 0 This field contains data bits used to compare against incoming data to the SMBus Slave Data Register (I/O Offset 0Ch).
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW Offset 9 - Programming Interface ................................... RW 7 Master IDE Capability........... fixed at 1 (Supported) 6-4 Reserved ........................................always reads 0 3 Programmable Indicator - Secondary ...... fixed at 1 Supports both modes (may be set to either mode by writing Rx42[6]) 2 Channel Operating Mode - Secondary 0 Compatibility Mode...............................
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW Offset 13-10 - Pri Data / Command Base Address..........RW Specifies an 8 byte I/O address space. Offset 2D-2C – Sub Vendor ID (0000h) ........................... RO The readback value may be changed by writing to RxD5-D4. 31-16 Reserved ..........................................always read 0 15-3 Port Address ....................................... default=01F0h 2-0 Fixed at 001b .....................................................
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW IDE-Controller-Specific Configuration Registers Offset 43 - FIFO Configuration (0Ah) ............................ RW 7-4 Reserved ........................................always reads 0 3-2 Primary Channel FIFO Threshold Determines the threshold required before the primary channel FIFO is flushed. 00 FIFO flushed when 1/4 full 01 FIFO flushed when 1/2 full 10 FIFO flushed when 3/4 full...................
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW Offset 45 - Miscellaneous Control 2 (20h)....................... RW 7 Reserved ........................................always reads 0 6 Interrupt Steering Swap Controls whether primary and secondary channel interrupts are swapped. 0 Primary channel interrupt is steered to IRQ14, Secondary channel is steered to IRQ15 . default 1 Primary channel interrupt is steered to IRQ15, Secondary channel interrupt steered to IRQ14 5 Reserved ...................
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW Offset 53-50 - UltraDMA Extended Timing Control ..... RW 31 Pri Drive 0 UltraDMA-Mode Enable Method 0 Enable by using “Set Feature” command .... def 1 Enable by setting bit-30 of this register 30 Pri Drive 0 UltraDMA-Mode Enable 0 Disable ................................................... default 1 Enable UltraDMA-Mode Operation 29 Pri Drive 0 Transfer Mode 0 DMA or PIO Mode ...............................
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW Offset 55 – IDE Clock Gating (00h) ................................ RW 7-2 Reserved ........................................always reads 0 1 Dynamic 100 / 133 MHz Clock Gating 0 Enable .................................................... default 1 Disable 0 Dynamic 66 MHz Clock Gating 0 Enable .................................................... default 1 Disable Offset 54 – UltraDMA FIFO Control (04h) ....................RW 7 Reserved ...........
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW Offset 70 – Primary IDE Status ....................................... RO 7 Interrupt Status................................................... RO 1 Primary channel interrupt request pending 6 Prefetch Buffer Status ........................................ RO 1 PIO Prefetch transaction in progress 5 Post Write Buffer Status..................................... RO 1 PIO Post Write transaction in progress 4 DMA Read Prefetch Status ..................
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW Device 17 Function 5 Registers - AC97 Audio Controller The audio controller interface is hardware compatible with AC97. The PCI configuration registers for the audio controller are located in the function 5 PCI configuration space. The I/O registers are located in the system I/O space. PCI Configuration Space Header Offset 1-0 - Vendor ID ...................................................... RO 7-0 Vendor ID .................
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW Audio-Specific PCI Configuration Registers Offset 40 – AC Link Interface Status .............................. RO 7-6 Reserved ........................................ always reads 0 5 Codec CID=11b Ready Status............................ RO 0 Codec Not Ready 1 Codec Ready (audio ctrlr can access codec) 4 Codec CID=10b Ready Status............................ RO 0 Codec Not Ready 1 Codec Ready (audio ctrlr can access codec) 3 Reserved ............
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW Offset 42 – Function Enable .............................................RW 7-6 Reserved ........................................ always reads 0 5 Function 5 Config Reg Rx2C Writable .............RW 0 Device 17 Function 5 Rx2C-2F RO ...... default 1 Device 17 Function 5 Rx2C-2F RW 4-0 Reserved ........................................ always reads 0 Offset 44 – MC97 Interface Control ................................
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW I/O Base 0 Regs – Audio Scatter / Gather DMA DXS Channel 0-3 SGD Registers (x = 0-3) I/O Offset x0 – DXS Channel x SGD Status.................RWC 7 SGD Active ......................................................... RO 0 SGD has completed or been terminated default 1 SGD Active 6-5 Reserved ........................................ always reads 0 4 Current SGD Index Equals Stop Index ............ RO 0 SGD index not equal to stop index........
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW I/O Offset x2 – DXS Left Channel x Volume (3Fh)........RW I/O Offset x3 – DXS Right Channel x Volume (3Fh) .....RW 7-6 Reserved (Do Not Program)............always write 0’s 5-0 Volume Control 000000 0 db … … 000111 -10.5 db … … 011111 -46.5 db … … 111111 Muted (instead of -94.5 db) .............. default I/O Offset xF-xC – DXS Chan x SGD Current Count....
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW Multichannel SGD Registers I/O Offset 40 – Multichannel SGD Status ....................RWC 7 SGD Active ......................................................... RO 0 SGD has completed or been terminated default 1 SGD Active 6-5 Reserved ........................................ always reads 0 4 Current SGD Index Equals Stop Index ............ RO 0 SGD index not equal to stop index........ default 1 SGD index being processed equals the stop index.
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW I/O Offset 42 – Multichannel SGD Format .....................RW 7 PCM Format Selects the PCM format used by the controller to process the incoming sample. 0 8-bit .................................................... default 1 16-bit 6-4 Number of Channels Supported 000 -reserved-...............................................
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW Write Channel 0 SGD Registers I/O Offset 60 – Write Channel 0 SGD Status...............RWC 7 SGD Active ......................................................... RO 0 SGD has completed or been terminated default 1 SGD Active 6 SGD Paused ......................................................... RO 0 SGD not paused..................................... default 1 SGD Paused 5 Reserved ........................................
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW I/O Offset 62 – Write Channel 0 SGD Format ...............RW 7 Reserved (Do Not Program)...............always write 0 6 Recording FIFO 0 Disable .................................................. default 1 Enable 5-0 Reserved ........................................ always reads 0 I/O Offset 63 – Write Channel 0 Input Select .................RW 7-3 Reserved ........................................
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW Write Channel 1 SGD Registers I/O Offset 70 – Write Channel 1 SGD Status...............RWC 7 SGD Active ......................................................... RO 0 SGD has completed or been terminated default 1 SGD Active 6 SGD Paused ......................................................... RO 0 SGD not paused..................................... default 1 SGD Paused 5 Reserved ........................................
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW I/O Offset 72 – Write Channel 1 SGD Format ...............RW 7 Reserved (Do Not Program)...............always write 0 6 Recording FIFO 0 Disable .................................................. default 1 Enable 5-0 Reserved ........................................ always reads 0 I/O Offset 73 – Write Channel 1 Input Select .................RW 7-3 Reserved ........................................
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW Codec Command / Status SGD Registers These registers are used to send commands to the codecs I/O Offset 83-80 – AC97 Controller Cmd (W) / Status (R) This register may be accessed from either function 5 or 6 31-30 Codec ID .........................................................RW 00 Select Codec CID = 00 01 Select Codec CID = 01 10 Select Codec CID = 10 11 Select Codec CID = 11 29 Codec 11 Data / Status / Index Valid ..................
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW Device 17 Function 6 Registers - AC97 Modem Controller The modem controller interface is hardware compatible with AC97. The PCI configuration registers for the modem controller are located in the function 6 PCI configuration space. The I/O registers are located in the system I/O space. PCI Configuration Space Header Offset 1-0 - Vendor ID (1106h)......................................... RO 7-0 Vendor ID .................
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW Modem-Specific PCI Configuration Registers Offset 40 – AC Link Interface Status .............................. RO 7-6 Reserved ........................................ always reads 0 5 Codec CID=11b Ready Status............................ RO 0 Codec Not Ready 1 Codec Ready (modem ctrlr can access codec) 4 Codec CID=10b Ready Status............................ RO 0 Codec Not Ready 1 Codec Ready (modem ctrlr can access codec) 3 Reserved ............
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW Offset 42 – Function Enable ............................................. RO This register is controlled through function 5 but may be read from function 6. 7-6 5 4-0 Reserved ........................................ always reads 0 Function 5 Config Reg Rx2C Writable ............. RO 0 Device 17 Function 5 Rx2C-2F RO ...... default 1 Device 17 Function 5 Rx2C-2F RW Reserved ........................................
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW I/O Base 0 Regs – Modem Scatter / Gather DMA Modem SGD Read Channel Registers I/O Offset 40 – Modem SGD Read Channel Status.....RWC 7 SGD Active ......................................................... RO 0 SGD has completed or been terminated default 1 SGD Active 6 SGD Paused ......................................................... RO 0 SGD not paused..................................... default 1 SGD Paused 5-4 Reserved ........................
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW Modem SGD Write Channel Registers I/O Offset 50 – Modem SGD Write Channel Status....... RO 7 SGD Active ......................................................... RO 0 SGD has completed or been terminated default 1 SGD Active 6 SGD Paused ......................................................... RO 0 SGD not paused..................................... default 1 SGD Paused 5-4 Reserved ........................................
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW Codec Command / Status SGD Registers These registers are used to send commands to the codecs Offset 83-80 – AC97 Controller Command (W) / Status (R) This register may be accessed from either function 5 or 6 31-30 Codec ID ......................................................... RW 00 Select Codec CID = 00 01 Select Codec CID = 01 10 Select Codec CID = 10 11 Select Codec CID = 11 29 Codec 11 Data / Status / Index Valid ..................
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW Device 18 Function 0 Registers - LAN All registers are located in the Device 18 Function 0 PCI configuration space of the VT8235. These registers are accessed through PCI configuration mechanism #1 via I/O address CF8 / CFC. PCI Configuration Space Header Offset 1-0 - Vendor ID = 1106h ........................................ RO Offset 3-2 - Device ID = 3065h.......................................... RO Offset 5-4 - Command.........................
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW Offset 43-42 – Power Mgmt Configuration (0002h) ....... RO 15-11 Power State In Which LAN Can Assert PME# ...... .............................................. default = 0 1xxxx PME# can be asserted from D3C x1xxx PME# can be asserted from D3H xx1xx PME# can be asserted from D2 xxx1x PME# can be asserted from D1 xxxx1 PME# can be asserted from D0 10 D2 PM State 0 Not Supported .......................................
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW LAN I/O Registers Offset 05-00 – Ethernet Address ......................................RW Unless the EEPROM is disabled, the Ethernet Address is loaded to this register from the EEPROM every time the system starts up. Offset 06 – Receive Control (00h) ....................................RW 7-5 Receive FIFO Threshold This field determines the threshold required before data in the receive FIFO is forwarded.
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW Offset 08 – Command 0 (00h)...........................................RW 7 Reserved ........................................ always reads 0 6 Receive Poll Demand ............................... default = 0 If this bit is set to 1, the Receive Descriptor (RD) will be polled once (this bit will be cleared by hardware after the polling is complete) 5 Transmit Poll Demand.............................
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW Offset 0C – Interrupt Status 0 (00h) ................................RW 7 CRC or Miss Packet Tally Counter Overflow Set if either counter overflows (both counters are 16 bits) 6 PCI Bus Error Set if PCI bus error occurred. 5 Receive Buffer Link Error Set when there is not enough buffer space for a packet requiring multiple buffers.
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW Offset 23-20 – Receive Status (0000 0000h).....................RW 31 Descriptor Owner 0 Descriptor Owned By Host (NIC cannot access descriptor) 1 Descriptor Owned by NIC (NIC can access descriptor) This bit has no default so must be set by the driver at initialization. 30-27 Reserved ........................................ always reads 0 26-16 Received Packet Length......................... RO, def = 0 15 Received Packet Successfully .............
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW Offset 43-40 – Transmit Status (0000 0000h)..................RW 31 Descriptor Owner 0 Descriptor Owned By Host (NIC cannot access descriptor) 1 Descriptor Owned by NIC (NIC can access descriptor) This bit has no default so must be set by the driver at initialization. 30-16 Reserved ........................................ always reads 0 15 Transmit Error................................. RO, default = 0 0 Transmit Successful ........................
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW Offset 6C – PHY Address (01h) .......................................RW 7-6 MII Management Polling Timer Interval (Polling PHY) 00 1024 MDC Clock Cycles ...................... default 01 512 MDC Clock Cycles 10 128 MDC Clock Cycles 11 64 MDC Clock Cycles MDC is an internal clock with a 960 ns cycle time. 5 Accelerate MDC Speed 0 Normal .................................................. default 1 4x Accelerated 4-0 Extended PHY Device Address.......
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW Offset 70 – MII Management Port Command (00h) ......RW 7 MII (PHY) Auto Polling 0 Disable .................................................. default 1 Enable (polling interval determined by Rx6C[7:6] ) 6 PHY Read Every time this bit is set to one, the PHY is read once. The address read is determined by Rx71[4:0] and the data is stored in Rx73-72. 5 PHY Write Every time this bit is set to one, the PHY is written once.
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW Offset 79 – Configuration 1 (00h).....................................RW 7 Transmit Frame Queueing 0 Enable (frames from the PCI bus can be queued in the transmit FIFO – a maximum of 2 packets may be queued) ..................... default 1 Disable 6 Data Parity Generation and Checking This bit controls whether PCI parity is enabled. 0 Enable....................................................
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW Offset 80 – Miscellaneous 1 (00h).....................................RW 7-4 Reserved ........................................ always reads 0 3 Full Duplex Flow Control 0 Disable .................................................. default 1 Enable 2 Half Duplex Flow Control 0 Disable .................................................. default 1 Enable 1 Soft Timer 0 Status / Start 0 Timer Counting .....................................
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW Offset 84 – MII Interrupt Status (00h) .........................RWC The bits in this register correspond to bits in the MII Interrupt Mask register (Rx86). An interrupt is generated when corresponding bits in both registers equal one. 7-4 3 2 1 0 Reserved (Do Not Program).................... default = 0 Transmit Data Write Buffer Queue Race .... def = 0 Set when write back race for transmit occurs.
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW Offset 95-94 – Suspend Mode MII Address (0000h).......RW 15-0 MII Address During Suspend ................. default = 0 Functionally, this field is the same as Rx71[4:0]. However, during suspend state this field is used because Rx71[4:0] cannot be accessed. Offset 96 – Suspend Mode PHY Address (00h) ..............RW 7-0 PHY Address During Suspend................ default = 0 This field stores the address of the PHY to access during suspend state.
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW Offset A0 – Wake On LAN Control Set (00h)................RW Offset A4 – Wake On LAN Control Clear (00h) ............
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW FUNCTIONAL DESCRIPTIONS Power Management Power Management Subsystem Overview Processor Bus States The power management function of the VT8235 is indicated in the following block diagram: The VT8235 supports the complete set of C0 to C3 processor states as specified in the Advanced Configuration and Power Interface (ACPI) specification (and defined in ACPI I/O space Registers 10-15): GP1 (Device Idle) Timer - SMI Events - SCI/SMI Events - Wake-
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW System Suspend States and Power Plane Control There are three power planes inside the VT8235. The first power plane (VSUS33) is always on unless turned off by the mechanical switch. The second power plane (VCC) is controlled by chip output SUSC# (also called “PSON”). The third plane (VCCRTC) is powered by the combination of the VSUS33 and the external battery (VBAT) for the integrated real time clock.
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW Power Management Events Three types of power management events are supported: 1) ACPI-required Fixed Events defined in the PM1a Status and PM1a Enable registers.
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW Legacy Power Management Timers In addition to the ACPI power management timer, the VT8235 includes the following four legacy power management timers: GP0 Timer: general purpose timer with primary event GP1 Timer: general purpose timer with peripheral event reload Secondary Event Timer: to monitor secondary events Conserve Mode Timer: Hardware-controlled return to standby The normal sequence of operations for a general purpose timer (GP0 or GP1) is
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings Symbol Parameter Min Max Unit Comment –55 125 ºC 0 85 ºC TS Storage Temperature TC Case Operating Temperature VCC Core Voltage –0.5 2.625 Volts 2.5V (VT8235L is 3.3V Core) VSUS25 Suspend Voltage – 2.5V –0.5 VCC + 0.3 Volts 2.5V VSUSUSB Suspend Voltage – USB –0.5 VCC + 0.3 Volts 2.5V VSUSMII Suspend Voltage – LAN –0.5 VCC + 0.3 Volts 2.
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW Register Bits Powered by VBAT Register Description RTC Rx0D[7] VBAT Voltage OK F0 Rx96[3:0] CPU Frequency Strapping Value PMIO Rx20[0] GPI0 Status PMIO Rx20[6] INTRUDER# Status PMIO Rx22[2] Enable SCI on KBC PME Asserted Register Bits Powered by VSUS25 Register Description F0 Rx81[2] RTC Enable Gated During Soft Off F0 Rx94[7:0] Power Well Control Register F0 Rx95[3:0] Misc Power Well Control Register PMIO Rx00[15,11,10,8] Wake
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW Power Requirements TC = 0 - 85°C VCC = VSUS25 = VSUSUSB = VSUSMII = VCCVK = VCCPLL = VCCUPLL = VCCRAM = 2.5V ±5%, VCC33 = VSUS33 = VCCUSB = VCCMII = 3.3V ±5%, VBAT = 3.3V +0.3 / –0.9V, VPDVREF = VSDVREF = VVLVREF = 0.9V ±5%, GND = 0V Symbol Parameter Typ Max Unit Condition ICC ICC33 ISUS33 ISUS25 ISUSUSB ISUSMII Power Supply Current – Core (3.3V) Power Supply Current – I/O (3.3V) Power Supply Current – Suspend (3.
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VT8235 V-Link South Bridge 7HFKQRORJLHV ,QF :H &RQQHFW PACKAGE MECHANICAL SPECIFICATIONS 24.00 REF Ø 1.00(3X) REF 4.00*45º (4X) Y W V L 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 = Date Code Year = Date Code Week = Chip Version = Lot Code 24.00 REF Part Number VT8235 YYWWVV TAIWAN LLLLLLLLL C M A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF PIN #1 CORNER Ø 0.10 S C Ø 0.25 S C A S B S Ø 0.60 ±0.10 (487x) 487-Pin BGA 25.00 27.00 ±0.20 1.