Product specifications
ProSavageDDR P4M266 – VT8751 P4 DDR SMA North Bridge
Revision 1.1, July 19, 2002 -2- Product Features
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• Advanced High-Performance DDR / SDR DRAM Controller
– DRAM interface pseudo-synchronous with host CPU (100 MHz) for most flexible configuration
– DRAM interface may be faster
than CPU by 33 MHz to allow use of 133 MHz memory with 100 MHz FSB clock
– Concurrent CPU, AGP, and V-Link access
– Supports SDR and DDR SDRAM memory types
– Clock Enable (CKE) control for SDRAM power reduction in high speed systems
– Mixed 16M / 32M / 64M x 8/16/32 DRAMs
– Supports 8 banks up to 4 GB DRAMs (512Mb x8/x16 DRAM technology)
– Flexible row and column addresses. 64-bit data width only
– LVTTL 3.3V DRAM interface with 5V-tolerant inputs for SDR SDRAM and 2.5V SSTL-2 DRAM interface for
DDR SDRAM
– Programmable I/O drive capability for MA, MD, and command signals
– Dual copies of MA and control signals for improved drive
– Optional ECC (single-bit error correction and multi-bit error detection)
or EC (error checking only) for DRAM integrity
– Two-bank interleaving for 16Mbit SDRAM support
– Two-bank and four bank interleaving for 64Mb, 128Mb, 256Mb, 512Mb SDRAM support
– Supports maximum 16-bank interleave (i.e., 16 pages open simultaneously); banks are allocated based on LRU
– Seamless DRAM command scheduling for maximum DRAM bus utilization
– (e.g., precharge other banks while accessing the current bank)
– Four cache lines (16 quadwords) of CPU to DRAM write buffers
– Four cache lines of CPU to DRAM read prefetch buffers
– Read around write capability for non-stalled CPU read
– Speculative DRAM read before snoop result
– Burst read and write operation
– Burst length 4 and 8 for SDR and DDR
– Supports DDR SDRAM CL 2/2.5/3 and 1T per command
– 1T and 2T command rate for SDR and DDR which can be specified bank by bank
– Decoupled and burst DRAM refresh with staggered RAS timing (CAS before RAS or self refresh)
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• Full Featured Accelerated Graphics Port (AGP) Controller
– Supports 266 MHz 4x and 133 MHz 2x transfer modes for AD and SBA signaling
– AGP specification v2.0 compliant
– Pseudo-synchronous with the host CPU bus with optimal skew control
– Supports SideBand Addressing (SBA) mode (non-multiplexed address / data)
– AGP pipelined split-transaction long-burst transfers up to 1GB/sec
– Eight level read request queue
– Four level posted-write request queue
– Thirty-two level (quadwords) read data FIFO (256 bytes)
– Sixteen level (quadwords) write data FIFO (128 bytes)
– Intelligent request reordering for maximum AGP bus utilization
– Supports Flush/Fence commands
– Graphics Address Relocation Table (GART)
– One level TLB structure
– Sixteen entry fully associative page table
– LRU replacement scheme
– Independent GART lookup control for host / AGP / PCI master accesses
– Windows 95 OSR-2 VXD and integrated Windows 98 / 2000 miniport driver support
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• High Resolution CRT RGB Interface
– 250 MHz RAMDAC on chip with Gamma Correction
– Horizontal / Vertical Sync outputs compliant with Monitor Power Management protocols
–I
2
C Serial Bus for DDC Monitor Communications
– Simultaneous display of CRT with TV or DVI Flat Panel Monitor