Product specifications

ProSavageDDR P4M266 – VT8751 P4 DDR SMA North Bridge
Revision 1.1, July 19, 2002 -1- Product Features
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Technologies, Inc.
PROSAVAGEDDR P4M266
CHIPSET
VT8751
Single-Chip SMA North Bridge
for Pentium 4 CPUs with 400 MHz Front Side Bus,
External 4x AGP Bus and
Integrated ProSavage8 AGP Graphics core
plus Advanced ECC Memory Controller
supporting PC2100 / PC1600 DDR SDRAM
and PC133 / PC100 SDR SDRAM
for Desktop PC Systems
PRODUCT FEATURES
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••
• Defines Integrated Solutions for Value PC Desktop Designs
– VIA VT8751 High Performance SMA North Bridge: Integrated Pentium 4 DDR VIA North Bridge and S3 Graphics
ProSavage8 2D/3D Graphics Controller with equivalent 8x AGP performance in a single chip
– 64-bit Advanced ECC Memory controller supporting PC2100/PC1600 DDR and PC100/PC133 SDR SDRAM
– Combines with VIA VT8233 V-Link South Bridge for integrated LAN, Audio, ATA100 IDE, and 6 USB ports
– 2.5V Core and AGTL+ I/O
– 37.5 x 37.5mm HSBGA (Ball Grid Array with Heat Spreader) package with 664 balls
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••
• High Performance CPU Interface
– Support for Intel™ Pentium 4 processors with 400 MHz (100 MHz QDR) CPU Front Side Bus (FSB)
– Built-in Phase Lock Loop circuitry for optimal skew control within and between clocking regions
– Nine outstanding transactions (eight In-Order Queue (IOQ) plus one output latch)
– Dynamic deferred transaction support
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••
• High Bandwidth 266MB/S 8-bit V-Link Host Controller
– Supports 66MHz V-Link Host interface with peak bandwidth of 266MB/S
– Operates at 2X or 4X modes
– Full duplex commands with separate command / strobe
– Request / Data split transaction
– Configurable outstanding transaction queue for Host to V-Link Client accesses
– Supports Defer / Defer-Reply transactions
– Transaction assurance for V-Link Host to Client access eliminates V-Link Host-Client Retry cycles
– Intelligent V-Link transaction protocol to eliminate data wait-state / throttle transfer latency
– All V-Link transactions for both Host and Client have a consistent view of transaction data depth and buffer size to
avoid data overflow
– Highly efficient V-Link arbitration with minimum overhead
– All V-Link transactions have predictable cycle length with known command / data duration