Product specifications

ProSavageDDR P4M266 – VT8751 P4 DDR SMA North Bridge
Revision 1.1, July 19, 2002 -61- Electrical Specifications
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Technologies, Inc.
Table 21. AC Timing – CPU Interface
Signal Reference Signal Setup Hold Min Delay Max Delay Unit
HD Bus HDS[3:0]# 0.55 0.55 0.85 0.80 ns
HA Bus HAS[1:0]# 0.50 0.55 1.6 1.6 ns
HREQ[4:0]# HAS0# 0.50 0.55 1.6 1.6 ns
ADS# HCLK 2.4 –0.20 ns
DBSY# HCLK 2.4 –0.20 ns
DRDY# HCLK 2.4 –0.20 ns
HIT# HCLK 2.4 –0.20 ns
HITM# HCLK 2.4 –0.20 ns
HLOCK# HCLK 2.4 –0.20 ns
Table 22. AC Timing – Memory Interface
Signal Reference Signal Setup Hold Min Delay Max Delay Unit
MD Bus DQS[7:0]# -1.2 2 1.10 1.05 ns
MA Bus – – – ns
SRAS# Bus – – – ns
SCAS# Bus – – – ns
SWE# Bus – – – ns
CS# Bus – – – ns
DQM Bus – – – ns
Table 23. AC Timing – V-Link Interface
Signal Reference Signal Setup Hold Min Delay Max Delay Unit
VAD Bus Strobes 0.45 0.45 1.1 1.1 ns
Table 24. AC Timing – AGP Interface
Signal Reference Signal Setup Hold Min Delay Max Delay Unit
GD Bus GDS[1:0]# 0.90 0.85 ns