Product specifications

ProSavageDDR P4M266 – VT8751 P4 DDR SMA North Bridge
Revision 1.1, July 19, 2002 -57- Functional Description
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Technologies, Inc.
External TV Encoder Interface
Figure 6 shows the interface to an external TV encoder
(BT868/869, VIA VT1621, or compatible device). The TV
outputs are generated whenever the clock input from the
decoder is present on the TVCLK pin, CRB0[3] = 1, and
CRB0[4] = 0. The encoder is controlled via the I
2
C interface.
TV monitor detection is also done via this interface. The TV
encoder interface and the flat panel interface are multiplexed
on common pins, so only one of the two (either the TV
interface or the flat panel interface) can be enabled at any
given time
Figure 6. External TV Encoder Interface
The P4M266 chipset VT8751 north bridge chip supports three
output formats as shown in Table 14. As shown in Figure 6,
P[11:0] on the encoder connect to TVD[11:0] on the VT8751
chip. The CLKI pin on the encoder connects to the TVCLKR
pin on the VT8751 chip.
SR35[5-4] = 00 SR35[5-4] = 01 SR35[5-4] = 10
Pin
CLK1
Rising
CLKI
Falling
CLK1
Rising
CLKI
Falling
CLK1
Rising
CLKI
Falling
P11G4R7B7G3R7G3
P10G3R6B6G2R6G2
P9 G2 R5 B5 G1 R5 G1
P8 B7 R4 B4 G0 R4 G0
P7 B6 R3 B3 R7 R3 B7
P6 B5 G7 B2 R6 R2 B6
P5 B4 G6 B1 R5 R1 B5
P4 B3 G5 B0 R4 R0 B4
P3 G0 R2 G7 R3 G7 B3
P2 B2 R1 G6 R2 G6 B2
P1 B1 R0 G5 R1 G5 B1
P0 B0 G1 G4 R0 G4 B0
Table 14. External TV Encoder Output Data
Formats
I
2
C Serial Communications Port
One serial communications port is implemented in a register
that can be accessed either via MMFF20 or CRA0. Bit 4 is set
to 1 to enable the interface. The clock is written to bit 0 (= 0)
anddatatobit1(=0),drivingtheSPCLK1andSPDAT1pins
low respectively. The state of the SPCLK1 pin can be read via
bit 2 and the state of the SPDAT1 pin can be read via bit 3.
The SPCLK1 and SPDAT1 pins are tri-stated when their
corresponding control bits are reset to 0, allowing other
devices to drive the serial bus.
This serial port is typically used for I2C interfacing. When
SPCLK1 and SPDAT1 are tri-stated, the P4M266 can detect
an I2C start condition (SPDAT1 driven low while SPCLK1 is
not driven low). This condition is generated by another I2C
master that wants control of the I2C bus. If bit 19 of
MMFF08 is set to 1, detection of a start condition generates an
interrupt and sets bit 3 of MMFF08 to 1. If bit 24 of MMFF08
is set to 1, the P4M266 drives SPCLK1 low to generate I2C
wait states until the Host can clear the interrupt and service the
I2C bus.
MS1TV
TV ENCODER
TVD[11:0]
TVCL
K
CLKO
P[11:0]
TVCLKR
CLKI
TVVS
VSYNC
TVHS
HSYNC
SPCLK1
SIC
SPDAT1
SID
TVBLAN
K
BLANK