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ProSavageDDR P4M266 – VT8751 P4 DDR SMA North Bridge

Revision 1.1, July 19, 2002 -56- Functional Description

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Technologies, Inc.

Display Interfaces

TFT Flat Panel DVI Interface

Figure 5 shows the hardware connections to a transceiver

conforming to the DVI 1.0 standard. This interface allows the

P4N266 to drive a TFT flat panel over considerable distance

and is active when CRB0[3] = 1 and CRB0[4] = 1. Panel

power sequencing is controlled by the receiver components.

Figure 5. DVI Interface

P4M266 provides the following panel detection capability. If

SR30[1] = 0 and the FPDET pin is properly connected to a

voltage source indicating the presence/absence of a panel,

SR30[1] will reflect the high/low state of this input. A read of

1 indicates that a powered-up panel is connected.

For proper flat panel output with a standard VGA primary

screen and the Streams Processor active, the following special

CR3A[4] = 1

CR67[3-2] = 01b (Streams Processor secondary and VGA

primary

CR67[7-4] = desired bits/pixel mode

CR90[3] = 1 (CR0 must be programmed before this is set to

1. Setting this bit is not required for 8 bit/pixel modes)

CR90[6] = 1 (this bit must also be set to 1 for 8 bit/pixel

modes)

MM8180 = 00000000h

These settings are required for correct automatic centering and

expansion with Streams Processor operation.

CRT Interface

P4M266 provides the following CRT interface signals:

• RED (analog red)

• GREEN (analog green)

• BLUE (analog blue)

• HSYNC (horizontal sync)

• VSYNC (vertical sync)

In addition, DDC2 monitor communications can be

implemented via the serial communications port controlled by

CRB1[4:0]. These bits control two-way communications over

the SPCLK2 (clock) and SPDAT2 (data) lines. The operation

is the same as described for the I

C serial communications

port section except that interrupts and wait states are not

supported.

DFPIF

DVI TRANSCEIVER

FPD[11:0]

D[11:0]

FPDE

FPVS

VSYNC

FPHS

HSYNC

FPCLK

IDCLK

FPDET

HOTPLUG