Product specifications

ProSavageDDR P4M266 – VT8751 P4 DDR SMA North Bridge
Revision 1.1, July 19, 2002 -55- Functional Description
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Display Memory
The P4M266 north bridge utilizes a Shared Memory
Architecture (SMA) for Frame Buffer Memory. SMA allows
system memory to be efficiently shared by the host CPU and
the P4M266 north bridge graphics controller. By default, no
system memory is allocated for the graphics frame buffer, but
up to 32 Mbytes may be allocated depending on user
preference, application requirements, and the total size of
system memory.
Note: Frame buffer memory is allocated from system memory
at bootup time. Changing the display settings to a resolution
requiring additional frame buffer memory will require a
system reboot to be performed.
Frame Buffer
Size
Dev 0 RxFB[6-4]
Register Setting
CR36[7-5] †
Register Setting
0 Mbytes 000 000
8 Mbytes 011 011
16 Mbytes 100 100
32 Mbytes 101 101
† For driver information only (not connected to hardware)
Table 13. Supported Frame Buffer Memory
Configurations
Interrupt Generation
Whatever the mode of operation (VGA or Enhanced), bit 4 of
CR32 must be set to 1 to enable interrupt generation. When
an enabled interrupt is generated, INTA# is pulled low unless
CR36[0] = 0 (MA2 pulled high at reset), for which case no
PCI interrupt line is claimed during PCI configuration.
When P4M266 graphics are being operated in VGA mode
(CR66[0] = 0), only vertical retrace can generate an interrupt.
This is enabled when CR11[5] = 0 and CR11[4] = 1. When an
interrupt occurs, it is cleared by writing a 0 to CR11[4]. The
interrupt must then be re-enabled by writing a 1 to the same
bit. Note that the BIOS clears both bit 4 and bit 5 of CR11
during power-on, a mode set, or a reset. Thus, interrupt
generation is disabled until bit 4 is set to 1.
In Enhanced mode (CR66[0] = 1 or 3D operation), interrupts
can be generated by vertical retrace, command or bus FIFO
overflow, command or bus FIFO empty, or by a BCI
command. These interrupts are enabled and cleared and their
status reported via MM8504. Serial port interrupts are
controlled via MMFF08. If interrupts are used, they should be
cleared before they are enabled.
Multiple interrupts can be enabled at the same time in
Enhanced mode. The interrupt pin will remain asserted until
all interrupt status bits are cleared.