Product specifications

ProSavageDDR P4M266 – VT8751 P4 DDR SMA North Bridge
Revision 1.1, July 19, 2002 -iv- Table of Contents
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Technologies, Inc.
LIST OF FIGURES
FIGURE 1. P4M266 CHIPSET SYSTEM BLOCK DIAGRAM .................................................................................................. 4
FIGURE 2. VT8751 / P4M266 BALL DIAGRAM (TOP VIEW)................................................................................................. 7
FIGURE 3. REFERENCE COMPONENT PLACEMENT USING THE P4M266 CHIPSET ............................................... 11
FIGURE 4. GRAPHICS APERTURE ADDRESS TRANSLATION......................................................................................... 41
FIGURE 5. DVI INTERFACE ...................................................................................................................................................... 56
FIGURE 6. EXTERNAL TV ENCODER INTERFACE ............................................................................................................ 57
FIGURE 7. MECHANICAL SPECIFICATIONS - 664-PIN HSBGA BALL GRID ARRAY PACKAGE WITH HEAT
SPREADER.............................................................................................................................................................................. 62
LIST OF TABLES
TABLE 1. SUPPORTED CRT SCREEN RESOLUTIONS.......................................................................................................... 6
TABLE 2. VT8751
PIN LIST (NUMERICAL ORDER)............................................................................................................... 8
TABLE 3. VT8751
PIN LIST (ALPHABETICAL ORDER)........................................................................................................ 9
TABLE 4. VT8751 / P4M266 PIN DESCRIPTIONS................................................................................................................... 10
TABLE 5. VT8751 / P4M266 REGISTERS.................................................................................................................................. 20
TABLE 6. SYSTEM MEMORY MAP.......................................................................................................................................... 32
TABLE 7. DEVICE 0 RX58 MA MAP TYPE ENCODING....................................................................................................... 33
TABLE 8. MEMORY ADDRESS MAPPING TABLE ............................................................................................................... 33
TABLE 9. DIMM MODULE CONFIGURATION...................................................................................................................... 38
TABLE 10. VGA/MDA MEMORY/IO REDIRECTION ........................................................................................................... 50
TABLE 11. DEFINITION OF STRAPPING BITS AT THE RISING EDGE OF RESET#.................................................... 53
TABLE 12. PCI SUBSYSTEM ID AND SUBSYSTEM VENDOR ID REGISTERS............................................................... 54
TABLE 13. SUPPORTED FRAME BUFFER MEMORY CONFIGURATIONS.................................................................... 55
TABLE 14. EXTERNAL TV ENCODER OUTPUT DATA FORMATS.................................................................................. 57
TABLE 15. ABSOLUTE MAXIMUM RATINGS....................................................................................................................... 58
TABLE 16. DC CHARACTERISTICS......................................................................................................................................... 58
TABLE 17. PACKAGE WEIGHT SPECIFICATIONS ............................................................................................................. 58
TABLE 18. POWER CHARACTERISTICS – INTERNAL AND INTERFACE DIGITAL LOGIC .................................... 59
TABLE 19. POWER CHARACTERISTICS – ANALOG AND REFERENCE VOLTAGES................................................ 60
TABLE 20. AC TIMING MIN / MAX CONDITIONS ............................................................................................................... 60
TABLE 21. AC TIMING – CPU INTERFACE ........................................................................................................................... 61
TABLE 22. AC TIMING – MEMORY INTERFACE ................................................................................................................ 61
TABLE 23. AC TIMING – V-LINK INTERFACE ..................................................................................................................... 61
TABLE 24. AC TIMING – AGP INTERFACE ........................................................................................................................... 61