Product specifications

ProSavageDDR P4M266 – VT8751 P4 DDR SMA North Bridge
Revision 1.1, July 19, 2002 -53- Functional Description
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FUNCTIONAL DESCRIPTION -INTEGRATED SAVAGE4GRAPHICS
Configuration Strapping
Certain P4M266 graphics functions have options that must be
selected and fixed at reset (before the register bits controlling
these functions can be programmed by software). This is
accomplished via power-on configuration strapping.
All strapping pins must be individually pulled high or low
through 10 KOhm resistors. These pull-ups and pull-downs
do not affect normal operation of the pins, but they do force
the pins to a definite state during reset. At the rising edge of
the reset signal, this state is sampled, the result is inverted and
the data loaded into the CR36, CR37, CRB0 and CRF0
registers. The data is used for system configuration. The
definitions of the graphics controller strapping bits at the
rising edge of the reset signal are shown in Table 11. Non-
graphics straps are described in the pinouts section of this
document (see the VAD pin descriptions).
Pin
Name
Ball #
CR Bit(s)
Value
Description
FPD9 E12 (n/a)
Graphics Test Mode
1 Enable
0 Disable
FPD7
FPD6
FPD5
FPD4
A12
C12
D12
E13
CRF0[3]
CRF0[2]
CRF0[1]
CRF0[0]
OEM-Defined Panel Type
FPD3 P4 CR37[3]
External XDCLK Input on XIN
1 Enable (use clock from XIN)
0 Disable (generate clock internally)
FPD2 A13 CRB0[7]
PCI Base Address Mapping
1 Address Mapping 1
0 Address Mapping 0 (PCI10, 14) (16M
assigned to PCI0; 128M assigned to
PCI14)
FPD1 B13 CR36[4]
IO Disable
1 Disable I/O access PCI04[0] ignored
0 Enable I/O access via PCI04[0] = 1.
FPD0 C13 CR36[0]
PCI Interrupt
1 Disable INTA# claim (00H in PCI3D)
0 Enable INTA# claim (01H in PCI3D)
Table 11. Definition of Strapping Bits at the Rising
Edge of RESET#
PCI Configuration and Integrated AGP
PCI Configuration
The P4M266 graphics Vendor ID register (Index 00H) in the
PCI Configuration space is hardwired to 5333H to specify S3
Graphics Incorporated as the vendor. The Device ID register
is hardwired to 8D04H.
Bits 10-9 of the Status register (Index 06H) are hardwired to
01b to specify medium DEVSEL timing. The Class Code
register (Index 08H) is hardwired to 30000xxH to specify that
the P4M266 is a VGA compatible device.
There are two MMIO address mappings, as determined by the
state of CRB0[7]. By default, CRB0[7] = 1, which selects
Mapping 0. This uses the PCI base addresses specified by
PCI10 and PCI14. 16 Mbytes of address space is claimed by
PCI10 and 128 Mbytes of address space is claimed by PCI14.
If the MA4 pin is strapped high at reset, a 0 is latched in
CRB0[7] and selects Mapping 1. This uses base addresses
PCI10 (same as Mapping 0), PCI14 (redefined from Mapping
0 to claim 16 Mbytes) and adds PCI18, PCI1C, PCI20 and
PCI24, each claiming 16 Mbytes. Thus, Mapping 1 allows the
address space claimed to be broken up into smaller blocks, as
required by some operating systems. The Base Address 0
register (Index 10H) defaults to address 7000 0000H. This is
the relocatable base address for memory-mapped I/O register
accessing.
PCI06[4] is hardwired to 1 to indicate a capabilities list is
available. PCI34[7-0] point to the PCI power management
registers starting at offset DC. The basic power states (D0-
D3) are supported as explained by the PCI Bus Power
Management Interface Specification, Revision 1.1.