Product specifications

ProSavageDDR P4M266 – VT8751 P4 DDR SMA North Bridge
Revision 1.1, July 19, 2002 -49- Device 1 Register Descriptions
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Device 1 Offset 18 - Primary Bus Number (00h)............RW
7-0 Primary Bus Number .............................. default = 0
This register is read write, but internally the chip always uses
bus 0 as the primary.
Device 1 Offset 19 - Secondary Bus Number (00h) ........RW
7-0 Secondary Bus Number........................... default = 0
Note: AGP must use these bits to convert Type 1 to Type 0.
Device 1 Offset 1A - Subordinate Bus Number (00h) ....RW
7-0 Primary Bus Number .............................. default = 0
Note: AGP must use these bits to decide if Type 1 to Type 1
command passing is allowed.
Device 1 Offset 1B – Secondary Latency Timer (00h) ....RO
7-0 Reserved ........................................ always reads 0
Device 1 Offset 1C - I/O Base (f0h)..................................RW
7-4 I/O Base AD[15:12].......................... default = 1111b
3-0 I/O Addressing Capability ...................... default = 0
Device 1 Offset 1D - I/O Limit (00h)................................RW
7-4 I/O Limit AD[15:12] ................................ default = 0
3-0 I/O Addressing Capability ...................... default = 0
Device 1 Offset 1F-1E - Secondary Status........................RO
15-0 Secondary Status
Rx44[4] = 0: these bits read back 0000h
Rx44[4] = 1: these bits read back same as Rx7-6
Device 1 Offset 21-20 - Memory Base (fff0h)..................RW
15-4 Memory Base AD[31:20]...................default = FFFh
3-0 Reserved ........................................ always reads 0
Device 1 Offset 23-22 - Memory Limit (Inclusive) (0000h) RW
15-4 Memory Limit AD[31:20] ....................... default = 0
3-0 Reserved ........................................ always reads 0
Device 1 Offset 25-24 - Prefetchable Memory Base (fff0h) RW
15-4 Prefetchable Memory Base AD[31:20]default = FFFh
3-0 Reserved ........................................ always reads 0
Device 1 Offset 27-26 - Prefetchable Memory Limit
(0000h) ...............................................................................RW
15-4 Prefetchable Memory Limit AD[31:20] . default = 0
3-0 Reserved ........................................ always reads 0
Device 1 Offset 34 - Capability Pointer (80h) ..................RO
Contains an offset from the start of configuration space.
7-0 AGP Capability List Pointer......... always reads 80h
Device 1 Offset 3F-3E – PCI-to-PCI Bridge Control
(0000h) .............................................................................. RW
15-4 Reserved ........................................always reads 0
3 VGA-Present on AGP
0 Forward VGA accesses to PCI Bus....... default
1 Forward VGA accesses to AGP Bus
Note: VGA addresses are memory A0000-BFFFFh
and I/O addresses 3B0-3BBh, 3C0-3CFh and 3D0-
3DFh (10-bit decode). "Mono" text mode uses
B0000-B7FFFh and "Color" Text Mode uses B8000-
BFFFFh. Graphics modes use Axxxxh. Mono VGA
uses I/O addresses 3Bx-3Cxh and Color VGA uses
3Cx-3Dxh. If an MDA is present, a VGA will not
use the 3Bxh I/O addresses and B0000-B7FFFh
memory space; if not, the VGA will use those
addresses to emulate MDA modes.
2 Block / Forward ISA I/O Addresses
0 Forward all I/O accesses to the AGP bus if
they are in the range defined by the I/O Base
and I/O Limit registers (device 1 offset 1C-
1D)
.................................................... default
1 Do not forward I/O accesses to the AGP bus
that are in the 100-3FFh address range even if
they are in the range defined by the I/O Base
and I/O Limit registers.
1-0 Reserved ........................................always reads 0