Product specifications

ProSavageDDR P4M266 – VT8751 P4 DDR SMA North Bridge
Revision 1.1, July 19, 2002 -48- Device 1 Register Descriptions
We Connect
We ConnectWe Connect
We Connect
Technologies, Inc.
Device 1 Register Descriptions
Device 1 PCI-to-PCI Bridge Header Registers
All registers are located in PCI configuration space. They
should be programmed using PCI configuration mechanism 1
through CF8 / CFC with bus number of 0 and function number
equal to 0 and device number
equal to one.
Device 1 Offset 1-0 - Vendor ID (1106h) ..........................RO
15-0 ID Code (reads 1106h to identify VIA Technologies)
Device 1 Offset 3-2 - Device ID (B091h) ...........................RO
15-0 ID Code (reads B091h to identify the P4M266 PCI-
to-PCI Bridge device)
Device 1 Offset 5-4 – Command (0007h).........................RW
15-10 Reserved ........................................ always reads 0
9 Fast Back-to-Back Cycle Enable ........................ RO
0 Fast back-to-back transactions only allowed to
the same agent........................................default
1 Fast back-to-back transactions allowed to
different agents
8SERR#Enable...................................................... RO
0 SERR# driver disabled...........................default
1 SERR# driver enabled
(SERR# is used to report ECC errors).
7 Address / Data Stepping...................................... RO
0 Device never does stepping....................default
1 Device always does stepping
6 Parity Error Response........................................RW
0 Ignore parity errors & continue..............default
1 Take normal action on detected parity errors
5 Reserved ........................................ always reads 0
4 Memory Write and Invalidate Command ......... RO
0 Bus masters must use Mem Write..........default
1 Bus masters may generate Mem Write & Inval
3 Special Cycle Monitoring .................................... RO
0 Does not monitor special cycles.............default
1 Monitors special cycles
2BusMaster.........................................................RW
0 Never behaves as a bus master
1 Enable to operate as a bus master on the
primary interface on behalf of a master on the
secondary interface ...............................default
1MemorySpace.....................................................RW
0 Does not respond to memory space
1 Enable memory space access ................default
0 I/O Space .........................................................RW
0 Does not respond to I/O space
1 Enable I/O space access ........................default
Device 1 Offset 7-6 - Status (Primary Bus) (0230h).....RWC
15 Detected Parity Error ........................always reads 0
14 Signaled System Error (SERR#).......always reads 0
13 Signaled Master Abort
0 No abort received .................................. default
1 Transaction aborted by the master with
Master-Abort (except Special Cycles)..............
....................................... write 1 to clear
12 Received Target Abort
0 No abort received .................................. default
1 Transaction aborted by the target with Target-
Abort ....................................... write 1 to clear
11 Signaled Target Abort .......................always reads 0
10-9 DEVSEL# Timing
00 Fast
01 Medium ...................................always reads 01
10 Slow
11 Reserved
8 Data Parity Error Detected ...............always reads 0
7 Fast Back-to-Back Capable...............always reads 0
6 User Definable Features ....................always reads 0
5 66MHz Capable..................................always reads 1
4 Supports New Capability list.............always reads 1
3-0 Reserved ........................................always reads 0
Device 1 Offset 8 - Revision ID (00h) ............................... RO
7-0 P4M266 Chip Revision Code (00=First Silicon)
Device 1 Offset 9 - Programming Interface (00h)........... RO
This register is defined in different ways for each Base/Sub-
Class Code value and is undefined for this type of device.
7-0 Interface Identifier...........................always reads 00
Device 1 Offset A - Sub Class Code (04h)........................ RO
7-0 Sub Class Code .reads 04 to indicate PCI-PCI Bridge
Device 1 Offset B - Base Class Code (06h)....................... RO
7-0 Base Class Code.. reads 06 to indicate Bridge Device
Device 1 Offset D - Latency Timer (00h) ......................... RO
7-0 Reserved ........................................always reads 0
Device 1 Offset E - Header Type (01h) ............................ RO
7-0 HeaderTypeCode............ reads 01: PCI-PCI Bridge
Device 1 Offset F - Built In Self Test (BIST) (00h) ......... RO
7 BIST Supported....... reads 0: no supported functions
6StartTest.......... write 1 to start but writes ignored
5-4 Reserved ........................................always reads 0
3-0 Response Code..........0 = test completed successfully