Product specifications

ProSavageDDR P4M266 – VT8751 P4 DDR SMA North Bridge
Revision 1.1, July 19, 2002 -47- Device 0 Register Descriptions
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Technologies, Inc.
Frame Buffer and High Memory Control
Device 0 Offset E0 – CPU Direct Access FB Base (00h) RW
7-1 CPU Direct Access FB Base Address[27:21] .def=0
0 CPU Direct Access Frame Buffer
0 Disable ...................................................default
1 Enable
Device 0 Offset E1 – CPU Direct Access FB Size (00h)..RW
7 Internal VGA
0 Disable ...................................................default
1 Enable
6-4 Frame Buffer Size
000 None .....................................................default
001 Reserved
010 Reserved
011 8MB
100 16MB
101 32MB
11x -reserved-
3-0 CPU Direct Access FB Base Address[31:28] .def=0
Device0OffsetE2–VGAArbitrationTimer1(00h)...RW
7-4 Timer to Promote High Priority Display ..... def = 0
3-0 Timer for Promoted High Priority Display .def=0
The fields above are defined in units of 16 MCLKs.
See note under VGA Timer 2 description).
Device 0 Offset E3 – SMA Control (00h) ........................RW
7-5 Reserved ........................................ always reads 0
4 Frame Buffer Address Conversion
0 Disable ...................................................default
1 Enable
Setting this bit further optimizes the MA table for
VGA frame buffer accesses according to the DRAM
page size in use. Setting this bit should improve
VGA performance especially in tiling address mode.
This but cannot be used at the same time as CPU
Direct Access FB mode. If used, this bit must be set
before enabling the internal VGA to prevent display
corruption.
3 Frame Buffer Page Close Prediction in Tiling
Address Mode
0 Disable ...................................................default
1 Enable
This feature automatically closes the FB DRAM
pages that are no longer needed in tiling address
mode. This bit can be set / cleared any time. This
feature will show maximum performance increase if
frame buffer address conversion is also enabled.
2-0 Frame Buffer Bank
Device 0 Offset E4 – Low Top Address Low (00h) ........ RW
7-4 Low Top Address Low............................. default = 0
3-0 DRAM Granularity
0 16M Total DRAM less than 4G ........ default
1 32M Total DRAM less than 8G
2 64M Total DRAM less than 16G
3 128M Total DRAM less than 32G
4 256M Total DRAM less than 64G
5-7 -reserved-
Device 0 Offset E5 – Low Top Address High (FFh) ...... RW
7-0 Low Top Address High........................default = FFh
Device 0 Offset E6 – SMM / APIC Decoding (01h) ....... RW
7-6 Reserved ........................................always reads 0
5 Reserved (Do Not Program).................... default = 0
4 I/O APIC Decoding
0 FECxxxxx accesses go to PCI............... default
1 FEC00000 to FEC7FFFF accesses go to PCI
FEC80000 to FECFFFFF accesses go to AGP
3 MSI (Processor Message) Support
0 Disable (master access to FEExxxxx will go to
PCI) .................................................... default
1 Enable (master access to FEExxxxx will be
passed to host side to do snoop)
2TopSMM
0 Disable................................................... default
1 Enable
1HighSMM
0 Disable................................................... default
1 Enable
0 Compatible SMM
0Disable
1 Enable................................................... default
Device0OffsetE8–VGAArbitrationTimer2(00h)...RW
7-4 Timer to Promote Low Priority Display .....def = 0
3-0 Timer for Promoted Low Priority Display .. def = 0
The fields above are defined in units of 16 MCLKs.
VGA timers 1 and 2 are access arbitration timers between the
display engine and the graphics engine. Normally the display
engine has lower priority than the graphics engine unless the
display buffer is below the threshold level where display
requests become high priority. The VGA Timers provide the
ability to override this deault behavior. These bits should be
set prior to turning on the VGA.
BIOS Scratch
Device 0 Offset F3-F4 – BIOS Scratch Registers ........... RW
7-0 No hardware function.............................. default = 0