Product specifications

ProSavageDDR P4M266 – VT8751 P4 DDR SMA North Bridge
Revision 1.1, July 19, 2002 -43- Device 0 Register Descriptions
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Technologies, Inc.
AGP Control (continued)
Device 0 Offset AD – AGP Miscellaneous Control (02h)RW
7 AGP Performance Improvement
0 Disable ...................................................default
1 Enable
6 Pipe Mode Performance Improvement
0 Disable ...................................................default
1 Enable
5 Input on AGP GD / GBE Pads
0 Disable ...................................................default
1 Enable
4 AGP Performance Improvement
0 Disable ...................................................default
1 Enable
3-0 AGP Data Phase Latency Timer ........ default = 02h
Device 0 Offset AE – AGP Miscellaneous Control (00h)RW
7-6 Reserved ........................................ always reads 0
5 4G Supported
0 4G not supported....................................default
1 4G supported
4 Fast Write Supported
0 Fast Write not supported ........................default
1 Fast Write supported
3 Reserved ........................................ always reads 0
2 4X Rate Supported
0 Disable ...................................................default
1 Enable
1-0 Reserved ........................................ always reads 0
Device 0 Offset B0 – AGP Pad Control / Status (8xh) ...RW
7 AGP 4x Strobe VREF Control
This bit is valid only when RxA8[2] = 1 (4x transfer
mode enabled), otherwise, STB VREF is AGPVREF.
0 STB VREF is STB# and vice versa
1 STB VREF is AGPVREF .....................default
The reference voltage is also determined by setting of
RxB2[1] (AGP Bus Voltage):
AGP Voltage
This Bit Strobe Reference Voltage
3.3V don’t care AGPVREF = 0.4 x 3.3V
1.5V 1 AGPVREF = 0.5 x 1.5V
1.5V 0 STB / STB#
6 AGP 4x Strobe & GD Pad Drive Strength
0 Drive strength set to compensation circuit
default ....................................................default
1 Drive strength controlled by RxB1[7-0]
5-3 AGP Compensation Circuit N Control Output.RO
2-0 AGP Compensation Circuit P Control Output .RO
Device 0 Offset B1 – AGP Drive Strength (63h) ............ RW
7-4 AGP Output Buffer Drive Strength N Ctrl....def=6
3-0 AGP Output Buffer Drive Strength P Ctrl ....def=3
Device 0 Offset B2 – AGP Pad Drive & Delay Ctrl (08h)RW
7 GD/GDS/GDS#/GBE Pad Control..........default = 0
SA / SBS
GD/GBE/GDS
0 VDDQ=1.5V: Normal Normal
VDDQ=3.3V: Delayed Normal
1 VDDQ=1.5V: Normal Delayed
VDDQ=3.3V Delayed Delayed
6 External AGP Pad Power Down
0 Disable................................................... default
1 Enable
5 GDS/GDS# Skew Relative to GD/GBE#
(see bit-2)
4 GD[31:16] Output Stagger Delay
0 No delay ................................................ default
1 Delay GD[31:16] by 1 ns
3 GD/GBE#, GDS, GDS# Slew Rate Control
0Disable
1 Enable................................................... default
2 GDS/GDS# Skew Relative to GD/GBE#
(part of a 2-bit field; this bit is lsb & bit-5 is msb)
00 GDS/GDS# early by 150 pS.................. default
01 GDS/GDS# center of GD
10 GDS/GDS# lags 150 pS from center of GD
10 GDS/GDS# lags 300 pS from center of GD
1 AGP Bus Voltage
0 1.5V .................................................... default
13.3V
0 GDS Output Delay
0 No delay ................................................ default
1 Delay GDS by 400 ps
(GDS & GDS# will be delayed 1 ns more if bit-4 = 1)
Device 0 Offset B3 – AGP Strobe Drive Strength (63h) RW
7-4 AGP Strobe Output Drive Strength N Ctrl ...def=6
3-0 AGP Strobe Output Drive Strength P Ctrl....def=3