Product specifications

ProSavageDDR P4M266 – VT8751 P4 DDR SMA North Bridge
Revision 1.1, July 19, 2002 -42- Device 0 Register Descriptions
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Technologies, Inc.
AGP Control
Device 0 Offset A3-A0 - AGP Capability Identifier
(0020C002h) ..........................................................RO
31-24 Reserved ...................................... always reads 00
23-20 Major Specification Revision ..... always reads 0010
Major rev # of AGP spec to which device conforms
19-16 Minor Specification Revision ..... always reads 0000
Minor rev # of AGP spec to which device conforms
15-8 Pointer to Next Item .... always reads C0h (last item)
7-0 AGP ID .. (always reads 02 to indicate it is AGP)
Device 0 Offset A7-A4 - AGP Status (1F000207h) ..........RO
31-24 Maximum AGP Requests................ always reads 1F
Max # of AGP requests the device can manage (32)
23-10 Reserved ........................................ always reads 0
9 Supports SideBand Addressing ........ always reads 1
8-6 Reserved ........................................ always reads 0
5 4G Supported ................. (can be written at RxAE[5]
4 Fast Write Supported.... (can be written at RxAE[4]
3 Reserved ........................................ always reads 0
2 4X Rate Supported ............................ always reads 1
1 2X Rate Supported ............................ always reads 1
0 1X Rate Supported ............................ always reads 1
Device 0 Offset AB-A8 - AGP Command (00000000h)..RW
31-24 Request Depth (reserved for target) ..always reads 0s
23-10 Reserved .......................................always reads 0s
9 SideBand Addressing Enable
0 Disable ...................................................default
1 Enable
8AGPEnable
0 Disable ...................................................default
1 Enable
7-6 Reserved .......................................always reads 0s
5 4G Enable
0 Disable ...................................................default
1 Enable
4 Fast Write Enable
0 Disable ...................................................default
1 Enable
3 Reserved .......................................always reads 0s
2 4X Mode Enable
0 Disable ...................................................default
1 Enable
1 2X Mode Enable
0 Disable ...................................................default
1 Enable
0 1X Mode Enable
0 Disable ...................................................default
1 Enable
Device 0 Offset AC - AGP Control (00h)........................ RW
7AGPDisable..........................................................RO
0 Disable................................................... default
1 Enable
This bit is latched from MA9 at the rising edge of
RESET#.
6 AGP Read Synchronization
0 Disable................................................... default
1 Enable
5 AGP Read Snoop DRAM Post-Write Buffer
0 Disable................................................... default
1 Enable
4 GREQ# Priority Becomes Higher When Arbiter is
Parked at AGP Master
0 Disable................................................... default
1 Enable
3 2X Rate Supported
0 Disable................................................... default
1 Enable
2 Fence / Flush
0 Disable – low priority requests may be
executed out of order. ............................ default
1 Enable – all normal priority AGP operations
will be executed in order
1 AGP Grant Parking Policy
0 Non-Parking Grant – if GFRM# or GPIPE# is
asserted, GGNT# is deasserted.............. default
1 Parking Grant – if GFRM# or GPIPE# is
asserted, GGNT# is not de-asserted until
GREQ# is deasserted or timeout
0 AGP to PCI Master or CPU to PCI Turnaround
Cycle
0 2T or 3T Timing.................................... default
11TTiming