Product specifications

ProSavageDDR P4M266 – VT8751 P4 DDR SMA North Bridge
Revision 1.1, July 19, 2002 -41- Device 0 Register Descriptions
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GART / Graphics Aperture Control
The function of the Graphics Address Relocation Table
(GART) is to translate virtual 32-bit addresses issued by an
AGP device into 4K-page based physical addresses for system
memory access. In this translation, the upper 20 bits (A31-
A12) are remapped, while the lower 12 address bits (A11-A0)
are used unchanged.
A one-level fully associative lookup scheme is used to
implement the address translation. In this scheme, the upper
20 bits of the virtual address are used to point to an entry in a
page table located in system memory. Each page table entry
contains the upper 20 bits of a physical address (a "physical
page" address). For simplicity, each page table entry is 4
bytes. The total size of the page table depends on the GART
range (called the "aperture size") which is programmable in
the P4M266.
This scheme is shown in the figure below.
31 12 11 0
Virtual Page Address Page Offset
index
TLB Base
Page Table
31 12 11 0
Physical Page Address Page Offset
Figure 4. Graphics Aperture Address Translation
Since address translation using the above scheme requires an
access to system memory, an on-chip cache (called a
"Translation Lookaside Buffer" or TLB) is utilized to enhance
performance. The TLB in the P4M266 contains 16 entries.
Address "misses" in the TLB require an access of system
memory to retrieve translation data. Entries in the TLB are
replaced using an LRU (Least Recently Used) algorithm.
Addresses are translated only for accesses within the
"Graphics Aperture" (GA). The Graphics Aperture can be any
power of two in size from 1MB to 256MB (i.e., 1MB, 2MB,
4MB, 8MB, etc). The base of the Graphics Aperture can be
anywhere in the system virtual address space on an address
boundary determined by the aperture size (e.g., if the aperture
size is 4MB, the base must be on a 4MB address boundary).
The Graphics Aperture Base is defined in register offset 10 of
device 0. The Graphics Aperture Size and TLB Table Base
are defined in the following register group (offsets 84 and 88
respectively) along with various control bits.
Device 0 Offset 83-80 - GART/TLB Control (00000000h) RW
31-16 Reserved ........................................always reads 0
15-8 Reserved (test mode status) .................................RO
7 Flush Page TLB
0 Disable................................................... default
1 Enable
6-0 Reserved ........................................always reads 0
Note: For any master access to the Graphics Aperture range,
snoop will not be performed.
Device 0 Offset 84 - Graphics Aperture Size (00h) ........ RW
7-0 Graphics Aperture Size
11111111 1M 1111000 16M
11111110 2M 1110000 32M
11111100 4M 11000000 64M
11111000 8M 10000000 128M
00000000 256M
Offset 85 – Write Policy (00h) ......................................... RW
7 Reserved ........................................always reads 0
6-4 Write Request Limit ................................ default = 0
3 Reserved ........................................always reads 0
2-0 Write Request Base .................................. default = 0
Offset 8B-88 - GA Translation Table Base (00000000h) RW
31-12 Graphics Aperture Translation Table Base.
Pointer to the base of the translation table in system
memory used to map addresses in the aperture range
(the pointer to the base of the "Directory" table).
11-2 Reserved ........................................always reads 0
1 Graphics Aperture Enable
0 Disable................................................... default
1 Enable
Note: To disable the Graphics Aperture, set this bit to
0 and set all bits of the Graphics Aperture Size to 0.
To enable the Graphics Aperture, set this bit to 1 and
program the Graphics Aperture Size to the desired
aperture size.
0 DRAM Power Reduction
0 Disable................................................... default
1 Enable (use only with 1 bank DRAM module)